View XRT83L3006_1506928.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt83l30 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator june 2006 rev. 1.0.1 general description the xrt83l30 is a fully integrated single-channel long-haul and short-haul line interface unit for t1(1.544mbps) 100 ? , e1(2.048mbps) 75 ? or 120 ? and j1 110 ? applications. in long-haul applications the xrt83l30 accepts signals that have passed through cables from 0 feet to over 6000 feet in length and have been attenuated by 0 to 45db at 772khz in t1 mode or 0 to 43db at 1024khz in e1 mode. in t1 applications, the xrt83l30 can generate five transmit pulse shapes to meet the short-haul digital cross-connect (dsx-1) template requirements as well as for channel service units (csu) line build ou t (lbo) filters of 0db, -7.5db, -15db and -22.5db as required by fcc rules. it also provides programmable transmit pulse generator that can be used for arbitrary output pulse shaping allowing performance improvement over a wide variety of conditions. the xrt83l30 provides both serial host microprocessor interface and hardware mode for programming and control. both b8zs and hdb3 encoding and decoding functions are included and can be disabled as required. on-chip crystal-less jitter attenuator with a 32 or 64 bit fifo can be placed either in the receive or the transmit path with loop bandwidths of less than 3hz. the xrt83l30 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. it supports internal impedance matching for 75 ?, 100 ?, 110 ? and 120 ? for both transmitter and receiver. for the receiver this is accomplished by internal resistors or through the combination of one single fixed value external resistor and program mable internal resistors. in the absence of the power supply, the transmit output and receive input are tri-stated allowing for redundancy applications. the chip includes an integrated programmable clock multiplier that can synthesize t1 or e1 master clocks from a variety of external clock sources. applications ? t1 digital cross-connects (dsx-1) ? isdn primary rate interface ? csu/dsu e1/t1/j1 interface ? t1/e1/j1 lan/wan routers ? public switching syst ems and pbx interfaces ? t1/e1/j1 multiplexer and channel banks features (see page 2) f igure 1. b lock d iagram of the xrt83l30 t1/e1/j1 liu (h ost m ode ) hw/host cs int ict txtest[0:2] insbpv tpos / tdata tneg / codes tclk qrpd rclk rneg / lcv rpos / rdata nlcd rlos rtip rring master clock synthesizer qrss pattern generator dmo ttip tring txon hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver drive monitor local analog loopback remote loopback digital loopback hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector network loop detector rx equalizer equalizer control ais detector los detector lbo[3:0] loopback enable ja select nlcd enable qrss enable sdo sclk sdi reset serial interface test taos enable mclke1 mclkt1 mclkout aisd
xrt83l30 2 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 features ? fully integrated single-channel long-haul and short-haul transceiver for e1,t1 or j1 applications. ? adaptive receive equalizer for cable attenuation of up to 45db for t1 and 43db for e1. ? programmable transmit pulse shaper for e1,t1 or j1 short-haul interfaces. ? five fixed transmit pulse settings for t1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shaping. ? programmable transmit line build-outs (lbo) for t1 long-haul application from 0db to -22.5db in three 7.5db steps. ? tri-state transmit ou tput and receive input capab ility for redundanc y applications ? selectable receiver sensitivity from 0 to 36db or 0 to 45db cable loss for t1 @772khz and 0 to 43db for e1 @1024khz. ? high receiver interference immunity ? receive monitor mode handles 0 to 29db resistive at tenuation along with 0 to 6db of cable attenuation for both t1 and e1 modes. ? supports 75 ? and 120 ? (e1), 100 ? (t1) and 110 ? (j1) applications. ? internal and external impedance matching for 75 ? ,100 ?, 110 ? and 120 ? . ? transmit return loss meets or exceeds etsi 300 166 standard ? on-chip digital clock recovery circ uit for high input jitter tolerance ? crystal-less digital jitter attenuator with 32-bit or 64-b it fifo selectable either in transmit or receive path ? on-chip frequency multiplier generates t1 or e1 master clocks from variety of external clock sources ? on-chip transmit short-circuit protection and limiting, and driver fa il monitor output (dmo) f igure 2. b lock d iagram of the xrt83l30 t1/e1/j1 liu (h ardware m ode ) hw/host gauge jasel1 jasel0 rxtsel txtsel tersel1 tersel0 rxres1 rxres0 ict mclke1 mclkt1 clksel[2:0] txtest[0:2] insbpv tpos / tdata tneg / codes tclk qrpd rclk rneg / lcv rpos / rdata nlcd rlos rtip rring master clock synthesizer qrss pattern generator dmo ttip tring txon hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver local analog loopback remote loopback digital loopback hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector network loop detector rx equalizer equalizer control ais detector los detector lbo[3:0] loopback enable ja select nlcd enable qrss enable harware control test jabw tratio sr/dr eqc[4:0] tclke rclke rxmute ataos drive monitor dfm mclkout loop1 loop0 aisd reset taos enable
xrt83l30 3 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator ? receive loss of signal (rlos) output ? on-chip hdb3/b8zs/ami encoder/decoder ? qrss pattern generation and detection for testing and monitoring ? error and bipolar violation insertion and detection ? receiver line attenuation indication output in 1db steps ? network loop-code detection for automatic loop-back activation/deactivation ? transmit all ones (taos) and in-band network loop up and down code generators ? supports analog, remote, digital and dual loop-back modes ? meets or exceeds t1 and e1 short-haul and long-haul network access specificati ons in itu g.703, g.775, g.736 and g.823; tr-tsy-000499; ansi t1.403 and t1.408; etsi 300-166 and at&t pub 62411 ? supports both hardware and serial microprocessor interface for programming ? programmable interrupt ? low power dissipation ? logic inputs accept either 3.3v or 5v levels ? single +3.3v supply operation ? 64 pin tqfp package ? -40c to +85c temperature range ordering information p art n umber p ackage o perating t emperature r ange xrt83l30iv 64 lead tqfp (10 x 10 x 1.4mm) -40 c to +85 c
xrt83l30 4 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 f igure 3. p in o ut of the xrt83l30 xrt83l30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rneg / lcv rpos / rdata ravdd rtip rring ragnd tagnd ttip tavdd tring dmo vddpll mclke1 mclkt1 gndpll mclkout agnd avdd loop0 loop1 sr / dr ataos tratio eqc0 / int eqc1 / cs eqc2 / sclk eqc3 / sdo eqc4 / sdi hw/host clksel0 clksel1 clksel2 jasel0 jasel1 jabw txtsel rxtsel tersel1 tersel0 reset qrpd aisd nlcd dgnd dvdd insbpv nlcde0 nlcde1 gauge rxmute rxres1 rxres0 rclke txtest2 txtest1 txtest0 tclke txon ict tclk tpos / tdata tneg / codes rlos rclk 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
xrt83l30 i rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator table of contents general description .......... ................ ................ ................. ................ .............. ......... 1 a pplications .............................................................................................................................. ................ 1 f eatures .............................................................................................................................. ..................... 1 figure 1. block diagram of the xrt83l30 t1/e1/j1 liu (host m ode) ................................................. 1 figure 2. block diagram of the xrt83l30 t1/e1/j1 liu (hardwar e mode) ........................................ 2 f eatures .............................................................................................................................. ..................... 2 ordering information .......................................................................................................... ..... 3 figure 3. pin out of the xrt83l30 ............................................................................................. ............ 4 table of contents ......... ................ ................. ................ ................. ................ ............ i pin descriptions by function .... ................. ................ ................. ................ ........... 5 s erial i nterface .............................................................................................................................. ......... 5 r eceiver .............................................................................................................................. ...................... 6 t ransmitter .............................................................................................................................. ................ 7 j itter a ttenuator .............................................................................................................................. ...... 9 c lock s ynthesizer .............................................................................................................................. ..... 9 r edundancy support ............................................................................................................................. 11 t erminations .............................................................................................................................. ............. 11 c ontrol function .............................................................................................................................. ..... 13 a larm f unction /o ther ........................................................................................................................... 14 p ower and ground .............................................................................................................................. ... 16 functional description .... ................ ................ ................. .............. .............. ......... 17 m aster c lock g enerator ..................................................................................................................... 17 figure 4. two input cl ock source ......... ................ ................ ................ ............. ............. ........... .......... 17 figure 5. one input clock source .............................................................................................. .......... 17 t able 1: m aster c lock g enerator ..................................................................................................... 18 receiver ........... ................. ................ ................ ................. .............. .............. ............. ... 18 r eceiver i nput .............................................................................................................................. .......... 18 r eceive m onitor m ode ........................................................................................................................... 19 r eceiver l oss of s ignal (rlos) ........................................................................................................... 19 figure 6. simplified diagram of -15db t1/e1 short haul mode and rlos condition ..................... 19 figure 7. simplified diagram of -29db t1/e1 gain mode and rlos condition ............................... 20 figure 8. simplified diagram of -36db t1/e1 long haul mode and rlos condition ..................... 20 figure 9. simplified diagram of extended rlos mode (e1 only) ..................................................... 21 r eceive hdb3/b8zs d ecoder ............................................................................................................... 21 r ecovered c lock (rclk) s ampling e dge ............................................................................................ 21 figure 10. receive clock and output data timing ............................................................................. 2 1 j itter a ttenuator .............................................................................................................................. .... 22 g apped c lock (ja m ust be e nabled in the t ransmit p ath ) ................................................................ 22 t able 2: m aximum g ap w idth for m ultiplexer /m apper a pplications .............................................. 22 a rbitrary p ulse g enerator ................................................................................................................. 23 figure 11. arbitrary puls e segment assignment ................................................................................ 23 transmitter ............. ................ ................ ................. .............. .............. .............. ......... 2 3 d igital d ata f ormat .............................................................................................................................. . 23 t ransmit c lock (tclk) s ampling e dge ................................................................................................ 23 figure 12. transmit clock and in put data timing .............................................................................. 24 t ransmit hdb3/b8zs e ncoder .............................................................................................................. 24 t able 3: e xamples of hdb3 e ncoding ................................................................................................. 24 t able 4: e xamples of b8zs e ncoding ................................................................................................. 24 d river f ailure m onitor (dmo) ............................................................................................................. 24 t ransmit p ulse s haper & l ine b uild o ut (lbo) circuit ...................................................................... 25 t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings ................................. 25 transmit and receive terminations ............... .............. .............. .............. ......... 27
xrt83l30 ii single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 receiver ...................................................................................................................... ......................... 27 internal receive termination mode .................... ......................................................................... ..................... 27 t able 6: r eceive t ermination c ontrol ................................................................................................ 27 figure 13. simplified diagram for the internal rece ive and transmit terminati on mode ............... 27 t able 7: r eceive t erminations .............................................................................................................. 28 figure 14. simplified diagram for t1 in the external termination m ode (rxtsel= 0) .................... 28 figure 15. simplified diagram for e1 in external termination mode (rxtsel= 0) .......................... 29 transmitter ................................................................................................................... ..................... 29 transmit termination mode ..................................................................................................... ......................... 29 t able 8: t ransmit t ermination c ontrol .............................................................................................. 29 t able 9: t ermination s elect c ontrol ................................................................................................. 29 external transmit termination mode ............................................................................................ ................... 29 t able 10: t ransmit t ermination c ontrol ............................................................................................ 30 t able 11: t ransmit t erminations .......................................................................................................... 30 redundancy applications ....................................................................................................... ...... 30 typical redundancy schemes .................................................................................................... . 31 figure 16. simplified bl ock diagram of the transm it section for 1:1 & 1+ 1 redundancy .. ............ 32 figure 17. simplified bl ock diagram - receive section for 1:1 and 1+1 redundancy ............... ..... 32 figure 18. simplified bl ock diagram - transmit section for n+ 1 redundancy ........... ................ ..... 33 figure 19. simplified bl ock diagram - receive section for n+1 redundancy ............ ................ ..... 34 p attern t ransmit and d etect f unction ............................................................................................... 35 t able 12: p attern transmission control ............................................................................................ 35 t ransmit a ll o nes (taos) ..................................................................................................................... 3 5 n etwork l oop c ode d etection and t ransmission ............................................................................... 35 t able 13: l oop -c ode d etection c ontrol ............................................................................................ 36 t ransmit and d etect q uasi -r andom s ignal s ource (tdqrss) ......................................................... 36 l oop -b ack m odes .............................................................................................................................. ...... 38 t able 14: l oop - back control in h ardware mode ............................................................................... 38 t able 15: l oop - back control in h ost mode ........................................................................................ 38 l ocal a nalog l oop -b ack (aloop) ........................................................................................................ 38 figure 20. local an alog loop-back signal flow ......... ................ ................ ................ ............. ........... . 38 r emote l oop -b ack (rloop) .................................................................................................................. 39 figure 21. remote loop-back mode wi th jitter attenuator sel ected in receive path .............. ......... 39 figure 22. remote loop-back mode wi th jitter attenuator sel ected in transmit pa th ............ ......... 39 d igital l oop -b ack (dloop) ................................................................................................................... 40 figure 23. digital loop-back m ode with jitter attenuator selected in transmit path ........... ............ 40 d ual l oop -b ack .............................................................................................................................. ........ 40 figure 24. signal flow in dual loop-back mode ................................................................................. .. 40 host mode serial interface operation ........ .............. .............. .............. ........ 41 u sing the m icroprocessor s erial i nterface ...................................................................................... 41 figure 25. microprocessor serial interface da ta structure ................................................................ 42 t able 16: m icroprocessor r egister a ddress .................................................................................... 43 t able 17: m icroprocessor r egister b it m ap ..................................................................................... 43 t able 18: m icroprocessor r egister #0 bit description .................................................................... 45 t able 19: m icroprocessor r egister #1 bit description .................................................................... 46 t able 20: m icroprocessor r egister #2 bit description .................................................................... 48 t able 21: m icroprocessor r egister #3 bit description .................................................................... 50 t able 22: m icroprocessor r egister #4 bit description .................................................................... 52 t able 23: m icroprocessor r egister #5 bit description .................................................................... 53 t able 24: m icroprocessor r egister #6 bit description .................................................................... 55 t able 25: m icroprocessor r egister #7 bit description .................................................................... 56 t able 26: m icroprocessor r egister #8 bit description .................................................................... 56 t able 27: m icroprocessor r egister #9 bit description .................................................................... 57 t able 28: m icroprocessor r egister #10 bit description .................................................................. 57 t able 29: m icroprocessor r egister #11 bit description .................................................................. 58
xrt83l30 iii rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 30: m icroprocessor r egister #12 bit description .................................................................. 58 t able 31: m icroprocessor r egister #13 bit description .................................................................. 59 t able 32: m icroprocessor r egister #14 bit description .................................................................. 59 t able 33: m icroprocessor r egister #15 bit description .................................................................. 60 t able 34: m icroprocessor r egister #16 bit description .................................................................. 61 t able 35: m icroprocessor r egister #17 bit description .................................................................. 62 t able 36: m icroprocessor r egister #18 bit description .................................................................. 63 e lectrical c haracteristics .................................................................................................................. 65 t able 37: a bsolute m aximum r atings ................................................................................................. 65 t able 38: dc d igital i nput and o utput e lectrical c haracteristics .............................................. 65 t able 39: xrt83l30 p ower c onsumption .......................................................................................... 65 t able 40: e1 r eceiver e lectrical c haracteristics ........................................................................... 66 t able 41: t1 r eceiver e lectrical c haracteristics ........................................................................... 67 t able 42: e1 t ransmit r eturn l oss r equirement .............................................................................. 67 t able 43: e1 t ransmitter e lectrical c haracteristics ..................................................................... 68 t able 44: t1 t ransmitter e lectrical c haracteristics ..................................................................... 68 figure 26. itu g.703 pulse temp late ........................................................................................... ........ 69 t able 45: t ransmit p ulse m ask s pecification .................................................................................... 69 figure 27. dsx-1 pulse template (normalized amplitude) ................................................................. 70 t able 46: dsx1 i nterface i solated p ulse m ask and c orner p oints ............................................... 70 t able 47: ac e lectrical c haracteristics .......................................................................................... 71 figure 28. transmit clock and in put data timing .............................................................................. 71 figure 29. receive clock and output data timing ............................................................................. 7 2 package dimensions ........ ................. ................ ................ ................. .............. ......... 73 64 lead thin quad flat pack .......................... .................................................................. 73 (10 x 10 x 1.4 mm tqfp) ............................................................................................................. 73 rev . 3.00 ........................................................................................................................ ............. 73 ordering information ................ ................ ................. ................ ................. ........... 74 t able 48. ......................................................................................................................... ....................... 74 r evision h istory .............................................................................................................................. ....... 74 notes ......................................................................................................................... ..................... 75
xrt83l30 5 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 pin descriptions by function serial interface s ignal n ame p in # t ype d escription hw/ host 20 i mode control input this pin is used for selecting hardware or host mode to control the device. leave this pin unconnected or tie ?high? to select hardware mode. for host mode, this pin must be tied ?low?. n ote : internally pulled ?high? with a 50k ? resistor. sdi eqc4 21 i serial data input in host mode, this pin is the data input for the serial interface. equalizer control input 4 hardware mode, see?control function? on page 13. sdo eqc3 22 o i serial data output in host mode, this pin is the output ?read ? data for the serial interface. equalizer control input 3 hardware mode, see?control function? on page 13. sclk eqc2 23 i serial interface clock input in host mode, this clock signal is used to control data ?read? or ?write? oper - ation for the serial interface. maximum clock frequency is 20mhz. equalizer control input 2 hardware mode, see?control function? on page 13. cs eqc1 24 i chip select input in host mode, tie this pin ?low? to enable communication with the device via the serial interface. equalizer control input 1 hardware mode, see?control function? on page 13. int eqc0 25 o i interrupt output (active "low") in host mode, this pin goes ?low? to indicate an alarm condition has occurred within the device. interrupt generation can be globally disabled by setting the gie bit to ?0? in the command control register. equalizer control input 0 hardware mode, see?control function? on page 13. n ote : this pin is an open drain output and requires an external 10k ? pull- up resistor.
xrt83l30 6 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator receiver s ignal n ame p in # t ype d escription rlos 63 o receiver loss of signal this signal is asserted ?high? for at least one rclk cycle to indicate loss of signal at the receive input. rclk 64 o receiver clock output rneg lcv 1 o receiver negative data output in dual-rail mode, this signal is the receiver negative-rail output data. line code violation output in single-rail mode, this signal goes ?high? for one rclk cycle to indicate a code violation is detected in the rece ived data. if ami coding is selected, every bipolar violation received will cause this pin to go ?high?. rpos rdata 2 o receiver positive data output in dual-rail mode, this signal is the receive positive-rail output data sent to the framer. receiver nrz data output in single-rail mode, this signal is the receive nrz format output data sent to the framer. rtip 4 i receiver differential tip positive input positive differential receive input from the line. rring 5 i receiver differential ring negative input negative differential receive input from the line. rxmute 50 i receive muting in hardware mode, connect this pin ?high? to mute rpos and rneg outputs to a ?low? state upon receipt of los condition to prevent data chattering. connect this pin to ?low? to disable muting function. n ote : internally pulled "low" with 50k ? resistor. rclke 53 i receive clock edge in hardware mode, with this pin set to ?high? the output receive data is updated on the falling edge of rclk. with this pin tied ?low?, output data is updated on the rising edge of rclk. n ote : internally pulled ?low? with a 50k ? resistor.
xrt83l30 7 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 transmitter s ignal n ame p in # t ype d escription ttip 8 o transmitter tip output positive differential transmit output to the line. tring 10 o transmitter ring output negative differential transmit output to the line. tpos tdata 61 i transmitter positive data input in dual-rail mode, this signal is the positive-rail input data for the transmitter. transmitter data input in single-rail mode, this pin is used as the nrz input data for the transmitter. n ote : internally pulled ?low? with a 50k ? resistor. tneg codes 62 i transmitter negative nrz data input in dual-rail mode, this signal is the negat ive-rail input data for the transmitter. in single-rail mode, this pi n can be left unconnected. coding select in hardware mode and with single-rail mode selected, connecting this pin "low" enables hdb3 in e1 or b8zs in t1 encoding and decoding. connect - ing this pin "high" selects ami data format. n ote : internally pulled ?low? with a 50k ? resistor. tclk 60 i transmitter clock input e1 rate at 2.048mhz 50ppm t1 rate at 1.544mhz 32ppm during normal operation, both in host mode and hardware mode, tclk is used for sampling input data at tpos/tdata and tneg/codes while mclk is used as the timing reference for the transmit pulse shaping circuit. tclke 57 i transmit clock edge in hardware mode, with this pin set to a "high", transmit input data is sam - pled at the rising edge of tclk. with this pin tied "low", input data are sam - pled at the falling edge of tclk. n ote : internally pulled ?low? with a 50k ? resistor. txon 58 i transmitter turn on in hardware mode, setting this pin "high" turns on the transmit section. in this mode, when txon = ?0?, ttip and tring driver outputs will be tri- stated. n otes : 1. internally pulled "low" with a 50k ? resistor. 2. in hardware mode only, the receiver is turned on at power-up.
xrt83l30 8 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator txtest2 txtest1 txtest0 54 55 56 i transmit test pattern pin 2 transmit test pattern pin 1 transmit test pattern pin 0 txtest[2:0] pins are used to generate and transmit test patterns according to the following table: taos (transmit all ones): activating this condition enables the transmis - sion of an all ones pattern.tclk must not be tied "low". tluc (transmit netw ork loop-up code): activating this condition enables the network loop-up code of "00001" to be transmitted to the line. when network loop-up code is being transmitted, the xrt83l30 will ignore the automatic loop-code detection and remote loop-back activation (nlcde1=?1?, nlcde0=?1?, if activated) in order to avoid activating remote digital loop-back automatically when t he remote terminal responds to the loop-back request. tldc (transmit network loop-down code): activating th is condition enables the network loop-down code of "001" to be transmitted to the line. tdqrss (transmit/detect quasi-random signal): setting txtest2=?1?, regardless of the state of txtest1 and txtest0, enables quasi-random signal source generation and detection. in a t1 system qrss pattern is a 2 20 -1 pseudo-random bit sequence (prbs) with no more than 14 consecu - tive zeros. in a e1 system, qrss is a 2 15 -1 prbs pattern. when txtest2 is ?1? and tdqrss is active, setting txtest0 to ?1? inverts the polarity of transmitted qrss patter n. resetting to "0" sends the qrss pattern with no inversion. when txtest2 is ?1? and tdqrss is active, transitions of txtest1 from "0" to "1" results in a bit error to be inserted in the transmitted qrss pattern. the state of this pin is sampled on the rising edge of tclk. to ensure the insertion of a bit error, this pin should be reset to a "0" before setting to a "1". when txtest2 is ?1?, txtest1 and txtest0 affect the transmitted qrss bit pattern independently. transmitter s ignal n ame p in #t ype d escription 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 transmit data taos tluc tldc test pattern txtest1 txtest0 txtest2 1 0 1 1 1 1 0 1 1 tdqrss tdqrss & invqrss tdqrss & insber tdqrss & invqrss & in s
xrt83l30 9 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 jitter attenuator s ignal n ame p in # t ype d escription jabw 46 i jitter attenuator bandwidth in hardware and e1 mode, when jabw=?0? the jitter attenuator bandwidth is 10hz (normal mode). setting jabw to ?1? selects a 1.5hz bandwidth for the jitter attenuator and the fifo length will be automatically set to 64 bits. in t1 mode the jitter attenuator bandwidth is always set to 3hz, and the state of this pin has no effect on the bandwidth. see table under jasel1 pin, below. n ote : internally pulled ?low? with a 50k ? resistor. jasel1 jasel0 47 48 i jitter attenuator select pin 1 jitter attenuator select pin 0 in hardware mode, jasel0, jasel1 and jabw pins are used to place the jitter attenuator in the transmit path, the receive path or to disable it and set the jitter attenuator bandwidth and fifo size per the following table. n ote : these pins are internally pulled "low" with 50k ? resistors. clock synthesizer s ignal n ame p in # t ype d escription mclke1 13 i e1 master clock input this input signal is an independent 2.048mhz clock for e1 system with required accuracy of better than 5 0ppm and a duty cycle of 40% to 60%. mclke1 is used in the e1 mode. its function is to provide internal timing for the pll clock recovery circuit, transmit pulse shaping, jitter attenuator block, reference clock during transmit all ones data and timing reference for the microprocessor in host mode operation. mclke1 is also input to a programm able frequency synthesizer that under the control of the clksel[2:0] inputs can be used to generate a master clock from an accurate external sour ce. in systems that have only one mas - ter clock source available (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. n otes : 1. see pin descriptions for pins clksel[2:0]. 2. internally pulled ?low? with a 50k ? resistor. disabled transmit receive receive ------ 32/32 32/32 64/64 ------ 3 3 3 ------ 10 10 10 0 0 1 1 0 1 0 1 0 0 0 0 disabled transmit receive receive -------- 32/64 32/64 64/64 ------ 3 3 3 ------ 1.5 1.5 1.5 0 0 1 1 0 1 0 1 1 1 1 1 ja path ja bw (hz) fifo size t1/e1 jasel1 jasel0 jabw t1 e1
xrt83l30 10 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator mclkt1 14 i t1 master clock input this signal is an independent 1.544mhz clock for t1 systems with required accuracy of better than 50ppm and duty cycle of 40% to 60%. mclkt1 input is used in the t1 mode. n otes : 1. see mclke1 description for further explanation for the usage of this pin. 2. internally pulled ?low? with a 50k ? resistor. mclkout 16 o synthesized master clock output this signal is the output of the master clock synthesizer pll which is at t1 or e1 rate based on the mode of operation. clksel2 clksel1 clksel0 17 18 19 i clock select input for master clock synthesizer pin 2 clock select input for master clock synthesizer pin 1 clock select input for master clock synthesizer pin 0 in hardware mode, clksel[2:0] are input signals to a programmable fre - quency synthesizer that can be used to generate a master clock from an external accurate clock source according to the following table. the mclkrate control signal is generated from the state of eqc[4:0] inputs. see table 5 for description of transmit equalizer control bits. in host mode, the state of these pins ar e ignored and the master frequency pll is controlled by the corresponding interface bits. n ote : internally pulled "low" with a 50k ? resistor. clock synthesizer s ignal n ame p in #t ype d escription 2048 2048 2048 1544 mclke1 (khz) 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 mclkt1 (khz) 1544 x x x 1544 x x x x x x x 2048 1544 2048 clkout (khz) 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 clksel0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 clksel1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 clksel2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 x x 2048 1544 0 1 0 1 mclkrate 1 0 1 0 0 1 0 1 1 0 1 0 0 1
xrt83l30 11 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 redundancy support s ignal n ame p in # t ype d escription dmo 11 o driver failure monitor this pin transitions "high" if a short circuit condition is detected in the trans - mit driver, or no transmit output puls e is detected for more than 128 tclk cycles. terminations s ignal n ame p in # t ype d escription gauge 49 i twisted pair cable wire gauge select in hardware mode, connect this pin "high" to select 26 gauge wire. connect this pin ?low? to select 22 and 24 gauge wire. n ote : internally pulled ?low? with a 50k ? resistor. tratio 26 i transmitter transformer ratio select in external termination mode, setting this pin "high" selects a transformer ratio of 1:2 for the transmitter. a "low" on this pin sets the transmitter trans - former ratio to 1:2.45. in the internal termination mode the transmitter trans - former ratio is permanently set to 1:2 and the state of this pin is ignored. n ote : internally pulled "low" with a 50k ? resistor. rxtsel 44 i receiver termination select in hardware mode when this pin is ?low? the receive line termination is determined only by the external resist or. when ?high?, the receive termina - tion is realized by internal resistors or the combination of internal and exter - nal resistors according to rxres[1:0]. these conditions are described in the following table: n ote : this pin is internally pulled "low" with a 50k ? resistor. txtsel 45 i transmit termination select in hardware mode when this pin is ?low? the transmit line termination is determined only by external resistor. when ?high?, the transmit termination is realized only by an internal resistor. these conditions are summarized in the following table: n ote : this pin is internally pulled "low" with a 50k ? resistor. rxtsel rx termination 0 1 external internal txtsel tx termination 0 1 external internal
xrt83l30 12 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator tersel1 tersel0 43 42 i termination impedance select pin 1 termination impedance select pin 0 in the hardware mode and in the internal termination mode (txtsel=?1? and/or rxtsel=?1?) tersel[1:0] contro l the transmit and receive termina - tion impedance according to the following table: in the internal termination mode, the receive termination is realized com - pletely by internal resistors or the combination of internal and one fixed exter - nal resistor (see description for rxres[1: 0] pins). in the internal termination mode the transformer ratio of 1:2 and 2:1 is required for the transmitter and receiver respectively with the transmi tter output ac coupled to the trans - former. n ote : this pin is internally pulled "low" with a 50k ? resistor. rxres1 rxres0 51 52 i receive external resistor control pin 1 receive external resistor control pin 0 in hardware mode, rxres[1:0] pins selects the required value of the exter - nal fixed resistor for the receiver according to the following table. this mode is only available in the internal impedance mode by pulling rxtsel ?high?. n ote : internally pulled ?low? with 50k ? resistor. terminations s ignal n ame p in #t ype d escription tersel1 0 1 ? 75 ? 0 1 0 termination tersel0 0 1 1 100 ? 120 ? 110 rxres1 0 0 rx fixed resistor no external fixed resistor 240? rxres0 0 1 1 1 210? 150 ? 0 1
xrt83l30 13 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 control function reset 41 i hardware reset (active "low") when this pin is tied ?low? for more than 10s, the device is put in the reset state. pulling reset ?low? while the ict pin is also ?low? will put the chip in fac - tory test mode. this condition should never happen during normal operation. n ote : internally pulled ?high? with a 50k ? resistor. sr/ dr 28 i single-rail/dual-rail data format in hardware mode, connect this pin "low" to select transmit and receive data format in dual-rail mode. in this mode, hdb3 or b8zs encoder and decoder are not available. connect this pin "high" to se lect single-rail data format. n ote : internally pulled "low" with a 50k ? resistor. loop1 loop0 29 30 i loop-back control pin 1 loop-back control pin 0 in hardware mode, loop[1:0] pins are used to control the loop-back func - tions according to the following table: n ote : internally pulled "low" with a 50k ? resistor. eqc4 sdi 21 i equalizer control input pin 4 in hardware mode, this pin together with eq c[3:0] are used for controlling the transmit pulse shaping, transmit lin e build-out (lbo), receive monitoring and also to select t1, e1 or j1 modes of operation. see table 5 for descrip - tion of transmit equalizer control bits. serial data input host mode, see?serial interface? on page 5. eqc3 sdo 22 i o equalizer control input pin 3 see eqc4/sdi description for further explanation for the usage of this pin. serial data output host mode, see?serial interface? on page 5. eqc2 sclk 23 i equalizer control input pin 2 see eqc4/sdi description for further explanation for the usage of this pin. serial interface clock input host mode, see?serial interface? on page 5. loop1 loop0 0 0 0 1 1 0 1 1 mode normal mode local loop-back remote loop-ba c digital loop-back
xrt83l30 14 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator eqc1 cs 24 i equalizer control input pin 1 see eqc4/sdi description for further explanation for the usage of this pin. chip select input host mode, see?serial interface? on page 5. eqc0 int 25 i o equalizer control input pin 0 see eqc4/sdi description for further explanation for the usage of this pin. interrupt output host mode, see?serial interface? on page 5. alarm function/other s ignal n ame p in # t ype d escription ataos 27 i automatic transmit ?all ones? pattern in hardware mode, a "high" level on this pin enables the automatic trans - mission of an "all ones" ami pattern from the transmitter when the receiver has detected an los condition. a "low" level on this pin disables this func - tion. n ote : this pin is internally pulled ?low? with a 50k ? resistor. ict 59 i in-circuit testing (active "low") when this pin is tied ?low?, all output pins are forced to a ?high? impedance state for in-circuit testing. pulling reset ?low? while ict pin is also ?low? will put the chip in factory test mode. this condition should never happen during normal operation. n ote : internally pulled ?high? with a 50k ? resistor. control function
xrt83l30 15 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 nlcde1 nlcde0 33 34 i network loop code detection enable pin 1 network loop code detection enable pin 0 nlcde[1:0] pins are used to contro l the loop-code detection according to the following table: when nlcde1=?0? and nclde0=?1?, or nlcde1=?1? and nlcde0=?0?, the chip is manually programed to monitor the receive data for the loop-up or loop-down code respectively. when the presence of the ?00001? or ?001? pattern is detected for more than 5 se conds, the nlcd pin is set to ?1? and the host has the option to activate the loop-back function manually. setting the nlcde1=?1? and nlcde0=?1? enables the automatic loop- code detection and remote-loop-back activation mode. as this mode is ini - tiated, the state of the nlcd pin is rese t to ?0? and the chip is programmed to monitor the receive data for the loop-up code. if the ?00001? pattern is detected for longer than 5 seconds, the nlcd pin is set to ?1?, remote loop- back is activated and the chip is aut omatically programed to monitor the receive data for the loop-down code. the nlcd pin stays ?high? even after the chip stops receiving the loop-up code. the remote loop-back condition is removed when the chip receives the loop-down code for more than 5 sec - onds or if the automatic loop-code detection mode is terminated. insbpv 35 i insert bipolar violation when this pin transitions from "0" to "1", a bipolar violation is inserted in the transmitted data stream. bipolar violatio n can be inserted either in the qrss pattern, or input data when operating in single-rail mode. the state of this pin is sampled on the rising edge of tclk. n ote : to ensure the insertion of a bipolar violation, this pin should be reset to a "0" prior to setting to a "1". alarm function/other s ignal n ame p in #t ype d escription nlcde1 nlcde0 function 0 0 disable loop-code detection 0 1 detect loop-up code in receive data 1 1 automatic loop-code detection 1 0 detect loop-down code in receive data
xrt83l30 16 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator nlcd 38 o network loop-code detection output pin this pin operates differently in the manual or the automatic network loop- code detection modes. in the manual loop-code detection mode (nlcde1 =?0? and nlcde0 =?1?, or nlcde1 =?1? and nlcde0 =?0?) this pin gets set to ?1? as soon as the loop-up (?00001?) or loop-down (?001?) code is detected in the receive data for longer than 5 seconds. the nlcd pin stays in the ?1? state for as long as the chip detects the presence of the loop-code in the receive data and it is reset to ?0? as soon as it stops receiving it. when the automatic loop-code detection mode (nlcde1 =?1? and nlcde0 =?1?) is initiated, the nlcd outpu t pin is reset to ?0? and the chip is programmed to monitor the receive input data for the loop-up code. the nlcd pin is set to a ?1? to indicate that the network loop code is detected for more than 5 seconds. simultaneously the remote loop-back condition is automatically activated and the chip is programmed to monitor the receive data for the network loop-down code. the nlcd pin stays in the ?1? state for as long as the remote loop-back condition is in effect even if the chip stops receiving the loop-up code. remo te loop-back is removed if the chip detects the ?001? pattern for longer than 5 seconds in the receive data. detecting the ?001? pattern also resu lts in resetting the nlcd output pin. aisd 39 o alarm indication signal detect output pin this pin is set to "1" to indicate that an all ones signal is detected by the receiver. the value of this pin is based on the current status of alarm indica - tion signal detector. qrpd 40 o quasi-random pattern de tection output pin this pin is set to "1" to indicate that the receiver is currently in synchroniza - tion with the qrss pattern. the value of this pin is based on the current sta - tus of quasi-random pattern detector. power and ground s ignal n ame p in # t ype d escription tagnd 7 **** transmitter analog ground tavdd 9 **** transmitter analog po sitive supply (3.3v + 5%) ragnd 6 **** receiver analog ground ravdd 3 **** receiver analog positive supply (3.3v 5%) vddpll 12 **** analog positive supply for master clock synthesizer pll (3.3v 5%) gndpll 15 **** analog ground for master clock synthesizer pll dvdd 36 **** digital positive su pply (3.3v 5%) avdd 31 **** analog positive su pply (3.3v 5%) dgnd 37 **** digital ground agnd 32 **** analog ground alarm function/other s ignal n ame p in #t ype d escription
xrt83l30 17 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 functional description the xrt83l30 is a fully integrated single channel long-haul and short-haul transceiver intended for t1, j1 or e1 systems. simplified block diag rams of the device are shown in figure 1 , host mode and figure 2 , hardware mode. the xrt83l30 can receive signals that have been attenuated from 0 to 36db at 772khz (0 to 6000 feet cable loss) for t1 and from 0 to 43db at 1024khz for e1 systems. in t1 applications, the xrt83l30 can generate five transmi t pulse shapes to meet the short-haul digital cross- connect (dsx-1) template requirement as well as four csu line build-out (lbo) filters of 0db, -7.5db, -15db and -22.5db as required by fcc rules. it also provid es programmable transmit output pulse generator that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. the operation and configuration of the xrt83l30 can be controlled through a serial microprocessor host interface or, by hardware control. master clock generator using a variety of external clock sources, the on-chip frequency synthesizer generat es the t1 (1.544mhz) or e1 (2.048mhz) master cloc ks necessary for the transmi t pulse shaping and receiv e clock recovery circuit. there are two master clock inputs mclke1 and mclkt1. in systems where both t1 and e1 master clocks are available these clocks can be connected to the respective pins. in systems that have only one master cl ock source available (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. t1 or e1 master clocks can be generated from 8khz, 16khz, 56khz, 64khz, 128k hz and 256khz external cl ocks under the control of clksel[2:0] inputs according to table 1 . n ote : eqc[4:0] determi ne the t1/e1 operating mode. see table 5 for details. f igure 4. t wo i nput c lock s ource f igure 5. o ne i nput c lock s ource mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz 2.048mhz +/-50ppm 1.544mhz +/-50ppm two input clock sources mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz one input clock source input clock options 8khz 16khz 56khz 64khz 128khz 256khz 1.544mhz 2.048mhz
xrt83l30 18 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator in host mode the programming is achieved through the corr esponding interface control bits, the state of the clksel[2:0] control bits an d the state of the mclkra te interface control bit. receiver receiver input at the receiver input, a cable attenuated ami signal can be coupled to the receiver through a capacitor or a 1:1 transformer. the input signal is first applied to a se lective equalizer for signal conditioning. the maximum equalizer gain is up to 36db for t1 and 43db for e1 modes. the equalized signal is subsequently applied to a peak detector which in turn controls t he equalizer settings and the data slicer. the slicer threshold for both e1 and t1 is typically set at 50% of the peak amplitude at the equalizer output. after the slicers, the digital representation of the ami signals are applied to t he clock and data recovery circuit. the recovered data subsequently goes through the jitter attenuator and decoder (if selected) for hdb3 or b8zs decoding before being applied to the rpos/rdata and rneg/lcv pins. clo ck recovery is accomplished by a digital phase- locked loop (dpll) which does not require any external components and can tolerate high levels of input jitter that meets or exceeds the itu-g.823 and tr-tsy000499 standards. in hardware mode only, this receive channel is turned on upon power-up and is always on. in host mode, the receiver can be turned on or off with the rxon bit. see?microprocessor register #2 bit description? on page 48. t able 1: m aster c lock g enerator mclke1 k h z mclkt1 k h z clksel2 clksel1 clksel0 mclkrate m aster c lock k h z 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544 8 x 0 1 0 0 2048 8 x 0 1 0 1 1544 16 x 0 1 1 0 2048 16 x 0 1 1 1 1544 56 x 1 0 0 0 2048 56 x 1 0 0 1 1544 64 x 1 0 1 0 2048 64 x 1 0 1 1 1544 128 x 1 1 0 0 2048 128 x 1 1 0 1 1544 256 x 1 1 1 0 2048 256 x 1 1 1 1 1544
xrt83l30 19 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 receive monitor mode in applications where monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29db, along with 0 to 6db cable attenuation for both t1 and e1 applications, refer to table 5 for details. this feature is available in both hardware and host modes. receiver loss of signal (rlos) for compatibility with itu g.775 require ments, the rlos monitoring func tion is implemented using both analog and digital detection schemes. if the analog rlos condition occurs, a digital detector is activated to count for 32 consecutive zeros in e1 (4096 bits in ex tended los mode, exlos = ?1?) or 175 consecutive zeros in t1 before rlos is asserted. rlos is cleared when t he input signal rises +3db (b uilt in hysteresis) above the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more than 16 consecutive zeros for e1. in t1 mode, rlos is cleared when the input signal rises +3db (built in hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more than 100 consecutive zeros in the data stream. when lo ss of signal occurs, rlos register indication and register status will change. if the rlos register enable is set high (en abled), the alarm will trigger an interrupt causing the interrupt pin ( int ) to go low. once the alarm status re gister has been read, it will automatically reset upon read (rur), and the int pin will return high. analog rlos setting the receiver input to -15db t1/e1 short haul mode by setting the receiver input to - 15db t1/e1 short haul mode, the equaliz er will detect the incoming amplitude and make adjustments by adding gain up to a maxi mum of +15db normalizing the t1/e1 input signal. n ote : this setting refers to cable loss (fre quency), not flat loss (resistive). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+15db), the receiver will declare rlos if the signal is atte nuated by an additi onal -9db. the total cable lo ss at rlos declaration is typically -24db (-15db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, the rlos will typically clear at a total cable atten uation of -21db. see figure 6 for a simplified diagram. setting the receiver input to -29db t1/e1 gain mode by setting the receiver input to -2 9db t1/e1 gain mode, the equalizer will detect the incomi ng amplitude and make adjustments by adding gain up to a maximum of +29db normalizing the t1/e1 input signal. n ote : this is the only setting that refers to flat loss (resi stive). all other modes refer to cable loss (frequency). f igure 6. s implified d iagram of -15db t1/e1 s hort h aul m ode and rlos c ondition normalized up to +15db max normalized up to +15db max declare los clear los -9db +3db clear los declare los +3db -9db
xrt83l30 20 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+29db), the receiver will declare rlos if the signal is atte nuated by an additi onal -9db. the total cable lo ss at rlos declaration is typically -38db (-29db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefore, th e rlos will typically clear at a to tal flat loss of -35db. see figure 7 for a simplified diagram. setting the receiver input to -36db t1/e1 long haul mode by setting the receiver input to -3 6db t1/e1 long haul mode , the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +36db normalizing the t1 input signal. this setting refers to cable loss (frequency), not fl at loss (resistive). once the t1/e1 input signal has been normalized to 0db by adding the maximum gain (+36 db), the receiver will declare rlos if the signal is attenuated by an additional -9db. the total cable loss at rlos declaratio n is typically -45db (-36db + -9db). a 3db hysteresis was designed so that transients will not trigger the rlos to clear. therefor e, the rlos will typically clear at a total cable attenuation of -42db. see figure 8 for a simplified diagram. e1 extended rlos e1: setting the receiver input to extended rlos by setting the receiver input to ex tended rlos, the equaliz er will detect the incomi ng amplitude and make adjustments by adding gain up to a maximum of +43db normalizing the e1 input signal. this setting refers to f igure 7. s implified d iagram of -29db t1/e1 g ain m ode and rlos c ondition f igure 8. s implified d iagram of -36db t1/e1 l ong h aul m ode and rlos c ondition normalized up to +29db max normalized up to +29db max declare los clear los -9db +3db clear los declare los +3db -9db normalized up to +36db max normalized up to +36db max declare los clear los -9db +3db clear los declare los +3db -9db
xrt83l30 21 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 cable loss (frequency), not flat loss (resistive). once the e1 input signal has been normalized to 0db by adding the maximum gain (+43db), the receiv er will declare rlos if the signal is attenuated by an additional -9db. the total cable loss at rlos declaration is typically -52db (-43db + -9db). a 3db hysteresis was designed so that transients will not trigge r the rlos to clear. therefore, the rlos will typically clear at a total cable attenuation of -49db. see figure 9 for a simplified diagram. receive hdb3/b8zs decoder the decoder function is available in both hardware and host modes by controlling the tneg/code pin or the code interface bit. the decoder func tion is only active in single-rail mo de. when selected, receive data in this mode will be decoded acco rding to hdb3 rules for e1 and b8zs for t1 systems. bipolar violations that do not conform to the coding scheme will be reported as line code violation at the rneg/lc v pin. the length of the lcv pulse is one rclk cycle for each code violati on. excessive number of zeros in the receive data stream is also reported as an error at the same output pin. if ami decoding is se lected in single rail mode, every bipolar violation in the rece ive data stream will be reported as an error at the rneg/lcv pin. recovered clock (rclk) sampling edge this feature is available in both hardware and host modes. in host mode, the sampling edge of rclk output can be changed through the interface control bit rclke. if a ?1? is written in the rclke interface bit, receive data output at rpos/rdata and rne g/lcv are updated on the falling edge of rclk. writing a ?0? to the rclke register, updates the receive data on the rising edge of rclk. in hardware mode the same feature is available under the control of the rclke pin. f igure 9. s implified d iagram of e xtended rlos mode (e1 o nly ) f igure 10. r eceive c lock and o utput d ata t iming normalized up to +45db max normalized up to +45db max declare los clear los -9db +3db clear los declare los +3db -9db rclk r rclk f rclk rpos or rneg r dy r ho
xrt83l30 22 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator jitter attenuator to reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive signal path. the jitter attenuator uses a data fifo (first in first out) with a programmable depth that can vary between 2x32 and 2x64. the jitter attenuator can also be placed in the transmit signal path or disabled altogether depending upon system requirements. the jitter attenuator, other than using the master clock as reference, requires no external components. with the ji tter attenuator selected, the typical throughput delay from input to output is 16 bits for 32 bit fifo size or 32 bits for 64 bit fifo size. when the read and write pointers of the fifo in the jitter attenuator are within tw o bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. when this situation occurs, the jitter a ttenuator will not attenuat e input jitter until the read/write pointer's position is outside the two bits window. under normal condition, the jitte r transfer characteristic meets the narrow bandwidth requirement as specified in itu- g.736, itu- i.431 and at&t pub 62411 standards. in t1 mode the jitter attenuator bandwidth is always set to 3hz. in e1 mode, the bandwidth can be reduced through the jabw control signal. when jabw is set ?hi gh? the bandwidth of the jitter attenuator is reduced from 10hz to 1.5hz. under this condition the fifo length is automatically set to 64 bits and the 32 bits fifo length will not be avail able in this mode. gapped clock (ja must be e nabled in the transmit path) the xrt83l30 liu is ideal for multip lexer or mapper applications where the network data crosses multiple timing domains. as the higher data rates are de-multipl exed down to t1 or e1 data, stuffing bits are removed which can leave gaps in the incoming data stream. if th e jitter attenuator is enabled in the transmit path, the 32-bit or 64-bit fifo is used to smooth the gapped cl ock into a steady t1 or e1 output. the maximum gap width is shown in table 2 . n ote : if the liu is used in a loop timing system, the jitte r attenuator should be enabled in the receive path. t able 2: m aximum g ap w idth for m ultiplexer /m apper a pplications fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui
xrt83l30 23 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 arbitrary pulse generator in t1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. each segment is set by a 7-bit binary word by pr ogramming the appropriate register. this allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. the msb (bit 7) is a sign-bit. if the sign-bit is set to ?1?, the segmen t will move in a positive direct ion relative to a flat line (zero) condition. if this sign-bit is set to ?0?, the segment will move in a negative direction relative to a flat line cond ition. a pulse with numbered segments is shown in figure 11 . n ote : by default, the arbitrary segments are programmed to 0x00h. the transmitter output will result in an all zero pattern to the line. transmitter digital data format both the transmitter and receiver can be configured to operate in dual or single-rail data formats. this feature is available under both hardware and host control modes. the dual or single-rail data format is determined by the state of the sr/ dr pin in hardware mode or sr/ dr interface bit in the host mode. in single-rail mode, transmit clock and nrz data are applied to tclk and tpos/tdata pins respectively. in single-rail and hardware mode the tneg/code input can be used as the codes function. with tneg/code tied ?low?, hdb3 or b8zs encoding and decoding are enabled for e1 and t1 modes respectively. with tneg/code tied ?high?, the ami coding scheme is selected. in both du al or single-rail modes of operations, the transmitter converts digital input data to a bipolar format before being transmitted to the line. transmit clock (tclk) sampling edge serial transmit data at tpos/tdata and tneg/code are clocked into the xrt83l30 under the synchronization of tclk. with a ?0? wr itten to the tclke interface bit, or by pulling the tclke pin ?low?, input data is sampled on the falling edge of tclk. the samp ling edge is inverted wit h a ?1? written to tclke interface bit, or by connec ting the tclke pin ?high?. f igure 11. a rbitrary p ulse s egment a ssignment 1 2 3 4 5 6 7 8 segment register 1 0xn8 2 0xn9 3 0xna 4 0xnb 5 0xnc 6 0xnd 7 0xne 8 0xnf
xrt83l30 24 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator transmit hdb3/b8zs encoder the encoder function is available in both hardware and host modes basis by contro lling the tneg/code pin or codes interface bit. the encoder is only available in single-rail mode. in e1 mode and with hdb3 encoding selected, any sequence with four or mo re consecutive zeros in the input se rial data from tpos/tdata, will be removed and replaced with 000v or b00v, where ?b? indi cates a pulse conforming with the bipolar rule and ?v? representing a pulse violating the rule. an example of hdb3 encoding is shown in table 3 . in a t1 system, an input data sequence with eight or more consecutive zero s will be removed and replaced using the b8zs encoding rule. an example of bipolar with 8 zero substitution (b8zs) encoding scheme is shown in table 4 . writing a ? 1 ? into the codes interface bit or connecting the tneg/code pin to a ?high? level selects the ami coding for both e1 or t1 systems. driver failure monitor (dmo) f igure 12. t ransmit c lock and i nput d ata t iming t able 3: e xamples of hdb3 e ncoding n umber of pulse before next 4 zeros n ext 4 bits input 0000 hdb3 (case1) odd 000v hdb3 (case2) even b00v t able 4: e xamples of b8zs e ncoding c ase 1 p receding p ulse n ext 8 b its input + 00000000 b8zs 000vb0vb ami output + 000+ -0- + c ase 2 input - 00000000 b8zs 000vb0vb ami output - 000- +0+ - tclk r tclk f tclk tpos/tdata or tneg t su t ho
xrt83l30 25 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 the driver monitor circuit is used to detect transmit dr iver failure by monitoring the activities at ttip and tring. driver failure may be caused by a short circui t in the primary transformer or system problems at the transmit input. if the transmitter has no output fo r more than 128 clock cycles, the corresponding dmo pin goes ?high? and remains ?high? until a valid transmit pulse is detected. in host mode, the failure of the transmit channel is reported in the corresponding interface bit. if the dmoie bit is also enabled, any transition on the dmo interface bit will generate an interrupt. the driver failure monitor is supported in both hardware and host modes. transmit pulse shaper & line build out (lbo) circuit the transmit pulse shaper circuit uses the high speed clock from the master timing generator to control the shape and width of the transmitted pulse. the internal high-speed timing generator eliminates the need for a tightly controlled transmit cl ock (tclk) duty cycle. with the jitter at tenuator not in the transmit path, the transmit output will generat e no more than 0.025unit interv al (ui) peak-to-peak jitter. in hardware mode, the state of the eqc[4:0] pins determine the transmit pulse shape. in host mode transmit pulse shape can be controlled using the interface bits eqc[4:0]. the chip su pports five fixed transmit pulse settings for t1 short- haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes. transmit line build-outs for t1 long-haul application are supported from 0db to -22.5db in three 7.5db steps. the choice of the transmit pulse shape and lbo under the control of the interface bits are summarized in table 5 . for csu lbo transmit pulse design information, refer to ansi t1.403-1993 network-to-customer installation specification, annex-e. n ote : eqc[4:0] determine the t1/e1 operat ing mode of the xrt83l30. when eqc4 = ?1? and eqc3 = ?1?, the xrt83l30 is in the e1 mode, otherwise it is in the t1/j1 mode. t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings eqc4 eqc3 eq c2 eqc1 eqc0 e1/t1 m ode & r eceive s ensitivity t ransmit lbo c able c oding 0 0 0 0 0 t1 long haul/36db 0db 100 ? / tp b8zs 0 0 0 0 1 t1 long haul/36db -7.5db 100 ? / tp b8zs 0 0 0 1 0 t1 long haul/36db -15db 100 ? / tp b8zs 0 0 0 1 1 t1 long haul/36db -22.5db 100 ? / tp b8zs 0 0 1 0 0 t1 long haul/45db 0db 100 ? / tp b8zs 0 0 1 0 1 t1 long haul/45db -7.5db 100 ? / tp b8zs 0 0 1 1 0 t1 long haul/45db -15db 100 ? / tp b8zs 0 0 1 1 1 t1 long haul/45db -22.5db 100 ? / tp b8zs 0 1 0 0 0 t1 short haul/15db 0-133 ft./ 0.6db 100 ? / tp b8zs 0 1 0 0 1 t1 short haul/15db 133-266 ft./ 1.2db 100 ? / tp b8zs 0 1 0 1 0 t1 short haul/15db 266-399 ft./ 1.8db 100 ? / tp b8zs 0 1 0 1 1 t1 short haul/15db 399-533 ft./ 2.4db 100 ? / tp b8zs 0 1 1 0 0 t1 short haul/15db 533-655 ft./ 3.0db 100 ? / tp b8zs 0 1 1 0 1 t1 short haul/15db arbitrary pulse 100 ? / tp b8zs
xrt83l30 26 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 0 1 1 1 0 t1 gain mode/29db 0-133 ft./ 0.6db 100 ? / tp b8zs 0 1 1 1 1 t1 gain mode/29db 133-266 ft./ 1.2db 100 ? / tp b8zs 1 0 0 0 0 t1 gain mode/29db 266-399 ft./ 1.8db 100 ? / tp b8zs 1 0 0 0 1 t1 gain mode/29db 399-533 ft./ 2.4db 100 ? / tp b8zs 1 0 0 1 0 t1 gain mode/29db 533-655 ft./ 3.0db 100 ? / tp b8zs 1 0 0 1 1 t1 gain mode/29db arbitrary pulse 100 ? / tp b8zs 1 0 1 0 0 t1 gain mode/29db 0db 100 ? / tp b8zs 1 0 1 0 1 t1 gain mode/29db -7.5db 100 ? / tp b8zs 1 0 1 1 0 t1 gain mode/29db -15db 100 ? / tp b8zs 1 0 1 1 1 t1 gain mode/29db -22.5db 100 ? / tp b8zs 1 1 0 0 0 e1 long haul/36db itu g.703 75 ? coax hdb3 1 1 0 0 1 e1 long haul/36db itu g.703 120 ? tp hdb3 1 1 0 1 0 e1 long haul/43db itu g.703 75 ? coax hdb3 1 1 0 1 1 e1 long haul/43db itu g.703 120 ? tp hdb3 1 1 1 0 0 e1 short haul itu g.703 75 ? coax hdb3 1 1 1 0 1 e1 short haul itu g.703 120 ? tp hdb3 1 1 1 1 0 e1 gain mode itu g.703 75 ? coax hdb3 1 1 1 1 1 e1 gain mode itu g.703 120 ? tp hdb3 t able 5: r eceive e qualizer c ontrol and t ransmit l ine b uild -o ut s ettings eqc4 eqc3 eq c2 eqc1 eqc0 e1/t1 m ode & r eceive s ensitivity t ransmit lbo c able c oding
xrt83l30 27 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 transmit and receive terminations the xrt83l30 is a ve rsatile liu that can be progr ammed to use one bill of ma terials (bom) for worldwide applications for t1, j1 and e1. for specific applications the internal terminations can be disabled to allow the use of existing components and/or designs. receiver i nternal r eceive t ermination m ode in hardware mode, rxtsel (pin 44) can be tied ?high? to select internal termination mode or tied ?low? to select external termination mode. by default the xrt83l3 0 is set for external termination mode at power up or at hardware reset. in host mode, bit 7 in the appropriate register, ( table 20, ?microprocessor register #1, bit description,? on page 47 ), is set ?high? to select the internal termination mode for the receive channel. if the internal termination mode (rxtsel = ?1?) is selected, the effective impedance for e1, t1 or j1 can be achieved either with an internal resistor or a combin ation of internal and exter nal resistors as shown in table 7 . t able 6: r eceive t ermination c ontrol rxtsel rx termination 0 external 1 internal f igure 13. s implified d iagram for the i nternal r eceive and t ransmit t ermination m ode t1 ttip tring 5 8 1:2 75 ? , 100 ? 110 ? or 120 ? 4 1 0.68 f r int r int ttip tring tx line driver t2 rtip rring 1 4 1:1 8 5 rtip rring rx equalizer r int tpos tneg tclk rpos rneg rclk 75 ? , 100 ? 110 ? or 120 ?
xrt83l30 28 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator figure 14 is a simplified diagram for t1 (100 ? ) in the external receive termination mode. figure 15 is a simplified diagram for e1 (75 ? ) in the external receive termination mode. t able 7: r eceive t erminations rxtsel tersel1 tersel0 rxres1 rxres0 r ext r int m ode 0 x x x x r ext t1/e1/j1 1 0 0 0 0 100 ? t1 1 0 1 0 0 110 ? j1 1 1 0 0 0 75 ? e1 1 1 1 0 0 120 ? e1 1 0 0 0 1 240 ? 172 ? t1 1 0 1 0 1 240 ? 204 ? j1 1 1 0 0 1 240 ? 108 ? e1 1 1 1 0 1 240 ? 240 ? e1 1 0 0 1 0 210 ? 192 ? t1 1 0 1 1 0 210 ? 232 ? j1 1 1 0 1 0 210 ? 116 ? e1 1 1 1 1 0 210 ? 280 ? e1 1 0 0 1 1 150 ? 300 ? t1 1 0 1 1 1 150 ? 412 ? j1 1 1 0 1 1 150 ? 150 ? e1 1 1 1 1 1 150 ? 600 ? e1 f igure 14. s implified d iagram for t1 in the e xternal t ermination m ode (rxtsel= 0) 3.1 ? 3.1 ? ttip tring rtip rring xrt83l30 liu 100 ? 100 ? 100 ? 1:2 or 1:2.45 1:1
xrt83l30 29 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 transmitter t ransmit t ermination m ode in hardware mode, txtsel (pin 45) can be tied ?high? to select internal termination mode or tied ?low? for external termination. in host mode, bit 6 in the appropriate register is set ?high? to select the internal termination mode for the transmit channel, see table 19, ?microprocessor register #1 bit description,? on page 46 . for internal termination, the transforme r turns ratio is always 1:2. in inte rnal mode, no external resistors are used. an external capacitor of 0.68 f is used for proper operation of the internal termination circuitry, see figure 13 . e xternal t ransmit t ermination m ode by default the xrt83l30 is set for exter nal termination mode at power up or at hardware reset. when external transmit termination mode is selected, the internal termination circuitry is disabled. the value of the external resistors is chosen for a specific applicatio n according to the turns ratio selected by tratio (pin 26) in hardware mode or bit 0 in the appropriate register in host mode, see table 10 and table 21, ?microprocessor register #3 bit description,? on page 50 . figure 14 is a simplified block diagram for t1 (100 ? ) in the external termination mode. figure 15 is a simplified block diagram for e1 (75 ? ) in the external termination mode. f igure 15. s implified d iagram for e1 in e xternal t ermination m ode (rxtsel= 0) t able 8: t ransmit t ermination c ontrol txtsel tx termination t x t ransformer r atio 0 external 1:2.45 1 internal 1:2 t able 9: t ermination s elect c ontrol tersel1 tersel0 termination 0 0 100 ? 0 1 110 ? 1 0 75 ? 1 1 120 ? 9.1 ? 9.1 ? ttip tring rtip rring 75 ? xrt83l30 liu 75 ? 75 ? 1:2 1:1
xrt83l30 30 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator table 11 summarizes the transmit terminations. redundancy applications telecommunication system de sign requires signal integr ity and reliability. when a t1/e1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivi ty to a backplane without losing data. system designers can achieve this by implementing common redundancy schemes with the xrt83l30 line interface unit (liu). the xrt83l30 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. these features allow system designers to implement redun dancy applications that ensur e reliability. the internal impedance mode eliminates the need for external rela ys when using the 1:1 and 1+1 redundancy schemes. t able 10: t ransmit t ermination c ontrol tratio t urns r atio 0 1:2 1 1:2.45 t able 11: t ransmit t erminations tersel1 tersel0 txtsel tratio r int ? n r ext ? c ext 0= external set by control bits n, r ext , and c ext are suggested settings 1= internal t1 100 ? 0 0 0 0 0 ? 2.45 3.1 ? 0 0 0 0 1 0 ? 2 3.1 ? 0 0 0 1 x 25 ? 2 0 ? 0.68 f j1 110 ? 0 1 0 0 0 ? 2.45 3.1 ? 0 0 1 0 1 0 ? 2 3.1 ? 0 0 1 1 x 27.5 ? 2 0 ? 0.68 f e1 75 ? 1 0 0 0 0 ? 2.45 6.2 ? 0 1 0 0 1 0 ? 2 9.1 ? 0 1 0 1 x 18.75 ? 2 0 ? 0.68 f e1 120 ? 1 1 0 0 0 ? 2.45 6.2 ? 0 1 1 0 1 0 ? 2 9.1 ? 0 1 1 1 x 30 ? 2 0 ? 0.68 f
xrt83l30 31 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 programming considerations in many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter on/off switching. in host mode, there are two bits in register 18 (12h) that control the transmitter outputs and the rx line impedance select, txoncntl (bit 5) and tercntl (bit 4). setting bit-5 (txoncntl) to a ?1? tr ansfers the co ntrol of the transmit on/o ff function to the txon hardware control pin (pin 58). setting bit-4 (tercntl) to a ?1? transfers the contro l of the rx line impedance select (rxtsel) to the rxtsel hardware control pin (pin 44). either mode works well with redundancy applications. the user can determine wh ich mode has the fastest switching time for a unique application. typical redundancy schemes 1:1 one backup card for every primary card (facility protection) 1+1 one backup card for every primary card (line protection) n+1one backup card for n primary cards 1:1 redundancy a 1:1 facility protection redundancy scheme has one backup card for every primary card. when using 1:1 redundancy, the backup card has its transmitters tri-stat ed and its receivers in high impedance. this eliminates the need for external re lays and provides one bill of materials for all inte rface modes of operation. the transmit and receive sections of the liu device are described separately. 1+1 redundancy a 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on the backup card are monitoring the receiver inputs. ther efore, the receivers on both cards need to be active. the transmit outputs require no external resistors. t he transmit and receive sections of the liu device are described separately. transmit 1:1 & 1+1 redundancy for 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for internal impedance mode. the transmitters on the backup card should be tri-stated. select the appropriate impedance for the desired mode of operation, t1/e1/j1 . a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted.
xrt83l30 32 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator receive 1:1 & 1+1 redundancy for 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for internal impedance mode. the receivers on the backup card should be prog rammed for external impedance mode. since there is no external resistor in th e circuit, the receivers on the backup ca rd will be high impedance. this key design feature eliminat es the need for relays a nd provides one bill of materials fo r all interface mo des of operation. select the impedance for the desired mode of operatio n, t1/e1/j1. to swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. see figure 17 for a simplified block diagram of the receive se ction for a 1:1 and 1+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. n+1 redundancy f igure 16. s implified b lock d iagram of the t ransmit s ection for 1:1 & 1+1 r edundancy f igure 17. s implified b lock d iagram - r eceive s ection for 1:1 and 1+1 r edundancy t1/e1 line backplane interface primary card backup card xrt83l30 xrt83l30 tx tx line interface card 0.68 f 0.68 f txtsel=1, internal txtsel=1, internal 1:2 rxtsel=0, external rxtsel=1, internal backplane interface primary card backup card xrt83l30 xrt83l30 rx line interface card t1/e1 line rx 1:1
xrt83l30 33 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 n+1 redundancy has one backup card for n primary card s. due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. the advantage of relays is that they create complete isolation between the primary cards and the ba ckup card. this allows all transmitters and receivers on the primary cards to be configur ed in internal im pedance mode, providing one bill of materials for all interface modes of operation. the transmit and receiv e sections of the xrt83l30 are described separately. transmit for n+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode providing one bill of materials for t1/e 1/j1. the transmitters on the backup card do not have to be tri-stated. to swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. a 0.68 f capacitor is used in series wi th ttip for blocking dc bias. see figure 18 for a simplified block diagram of the transmit section for an n+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 18. s implified b lock d iagram - t ransmit s ection for n+1 r edundancy backplane interface primary card xrt83l30 tx line interface card 0.68 f t1/e1 line primary card xrt83l30 tx primary card xrt83l30 tx backup card xrt83l30 tx t1/e1 line t1/e1 line txtsel=1, internal txtsel=1, internal txtsel=1, internal txtsel=1, internal 1:2 0.68 f 0.68 f 0.68 f 1:2 1:2
xrt83l30 34 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator receive for n+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. the receivers on the backup card should be programmed for external impedance mode. since there is no external resistor in the circuit, th e receivers on the backup card will be hi gh impedance. select the impedance for the desired mode of operation, t1/e1/j1. to swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. see figure 19 . for a simplified block diagram of the receive section for a n+1 redundancy scheme. n ote : for simplification, the over volta ge protection circuitry was omitted. f igure 19. s implified b lock d iagram - r eceive s ection for n+1 r edundancy backplane interface primary card xrt83l30 rx line interface card primary card xrt83l30 rx primary card xrt83l30 rx backup card xrt83l30 rx rxtsel=1, internal rxtsel=1, internal rxtsel=1, internal rxtsel=1, external t1/e1 line t1/e1 line t1/e1 line 1:1 1:1 1:1
xrt83l30 35 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 pattern transmit and detect function several test and diagnostic patterns can be generated and detected by the chip. in hardware mode the channel can be programmed to transmit an all ones pattern by applying a ?high? level to the corresponding taos pin. in host mode, the three interface bits txtest[2:0] control the pattern generation and detection according to table 12 . transmit all ones (taos) this feature is available in both hardware and host modes. when the hardware pins or interface bits txtest2="0", txtest1="0" and txtest0="1", the transmitter ignores input from tpos/tdata and tneg pins and sends a continuous ami encoded all ones signal to the line using tclk clock as the reference. when tclk is not available, mclk is used. in addition, when the hardware pin or the interface bit ataos is activated, the chip will automatically tr ansmit the all ones data when the re ceiver detects an rlos condition. the operation of this feature requires that tclk not be tied "low". network loop code detection and transmission this feature is available in both hardware and host modes. when the hardware pins or interface bits txtest2="0", txtest1="1" and txtest 0="0" the chip is enabled to transmit the "00001" network loop-up code from a request for a loop-back condition from the remote terminal. simultaneously setting the interface bits nlcde1="0" and nlcde0="1" enables the network loop-up code detection in the receiver. if the "00001" network loop-up code is detected in the receive data for longer than 5 seconds, the nlcd bit in the interface register is set indicating that the remote terminal has activated remote loop-back and the chip is receiving its own transmitted data. when network l oop-up code is being tr ansmitted the xrt83l30 will ignore the auto - matic loop-code detection and remote loop-back activa tion (nlcde1=?1?, nlcde0 =?1?, if activated) in order to avoid activating remote digital loop-back auto matically when the remote terminal responds to the loop-back request. when txtest2="0", txtest1="1" and txtest0="1" the chip is enabled to transmit the network loop-down code "001" from the transmitter requesting the remo te terminal the removal of the loop-back condition. in both hardware and host modes the receiver is capable of monitori ng the contents of the receive data for the presence of loop-up or loop-down code from the remote terminal. the hardware pins or interface bits t able 12: p attern transmission control txtest2 txtest1 txtest0 t est p attern 0 0 0 transmit data 0 0 1 taos 0 1 0 tluc 0 1 1 tldc 1 0 0 tdqrss 1 0 1 tdqrss & invqrss 1 1 0 tdqrss & insber 1 1 1 tdqrss & invqrss & insber
xrt83l30 36 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator nlcde[1:0] control the loop-code detection according to table 13 . setting the hardware pins or interface bits nlcde1="0" and nl cde0="1" activates the detection of the loop- up code in the receive data. if the "00001" network loop-up code is detected in the receive data for longer than 5 seconds the nlcd interface bit is set to "1" and st ays in this state for as long as the receiver continues to receive the network loop-up code. in this mode if the nlcd interrup t is enabled, the ch ip will initiate an interrupt on every transition of nlcd. the host has the option to ignore the request from the remote terminal, or to respond to the request and manually activate re mote loop-back. the host can subsequently activate the detection of the loop-down code by setting nlcde1="1" and nlcde0="0". in this case, receiving the "001" loop-down code for l onger than 5 seconds will set the nlcd bit to "1" and if the nlcd interr upt is enabled, the chip will initiate an interrupt on every tr ansition of nlcd. the host can respond to the request from the remote terminal and remove loop-back condition. in the manual network loop-up (nlcde1="0" and nlcde0="1") and loop-down (nlcde 1="1" and nlcde0="0") code detection modes, the nlcd pin or interface bit will be set to "1" upon rece iving the corresponding code in excess of 5 seconds in the receive data. in host mode the chip will initiate an inte rrupt any time the stat us of the nlcd bit changes and the network loop-code interrupt is enabled. setting the hardware pins or interface bits nlcde1="1" and nlcde0="1" enables the automatic loop-code detection and remote loop-back activation mode if, tx test[2:0] is not equal to ?110?. as this mode is initiated, the state of the nlcd pin or interface bit is reset to "0" and the chip is programmed to monitor the receive input data for the loop-up code. if the "00001" network loop-up code is detected in the receive data for longer than 5 seconds in addition to setting t he nlcd pin or interface bit, remote loop-back is automatically activated. the chip stays in remote loop-back even if it stops receiving the "00001" pattern. after the chip detects the loop-up code, sets the nlcd pin (b it) and enters remote loop -back, it automatically starts monitoring the receive data for the loop-down code. in this mode however, the nlcd pin (bit) stays set even if the receiver stops receiving the loop-up code, wh ich is an indication to the host that the remote loop- back is still in effect. remote loop -back is removed if the chip detects the "001" l oop-down code for longer than 5 seconds. detecting the "001" code also results in resetting the nlcd pin (bit) and initiating an interrupt. the remote loop-back can also be removed by taking the chip out of the automatic detection mode by programming it to operate in a different state. the chip will not resp ond to remote loop-b ack request if an analog loop-back is activated locally. when programmed in automatic detection mode the nlcd pin (bit) stays "high" for the whole time the remote loop-back is activated and in the host mode it initiates an interrupt any time the status of the nlcd bit changes provid ed the network loop-code interrupt is enabled. transmit and detect quasi-rand om signal source (tdqrss) the xrt83l30 includes a qrss pattern generation and de tection block for diagnostic purposes that can be activated only in the host mode by setting the interface bits txtest2=?1?, txtest1=?0? and txtest0=?0?. for t1 systems, the qrss pattern is a 2 20 -1pseudo-random bit sequence (prbs) with no more than 14 consecutive zeros. for e1 sy stems, the qrss pattern is 2 15 -1 prbs with an inverted output. with qrss and analog local loop-back enabled simultaneously, and by mo nitoring the status of the qrpd interface bit, all main functional blocks within th e transceiver can be verified. when the receiver achieves qrss sy nchronization with fewer than 4 errors in a 128 bits window, qrpd changes from ?low? to ?high?. after pattern synchronization, any bit erro r will cause qrpd to go ?low? for one clock cycle. if the qrpdie bit is enabled, any tran sition on the qrpd bit will generate an interrupt. t able 13: l oop -c ode d etection c ontrol nlcde1 nlcde0 condition 0 0 disable loop-code detection 0 1 detect loop-up code in receive data 1 0 detect loop-down code in receive data 1 1 automatic loop-code detection and remote loop-back activation
xrt83l30 37 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 with tdqrss activated, a bit error can be inserted in the transmitted qrss pattern by transitioning the insber interface bit from ?0? to ?1?. bipolar violation ca n also be inserted either in the qrss pattern, or input data when operating in the single-rail mode by transitioning t he insbpv interface bit from ?0? to ?1?. the state of insber and insbpv bits are sampled on the rising edge of the tclk. to in sure the insertion of the bit error or bipolar violation, a ?0? should be written in these bit locations before writing a ?1?.
xrt83l30 38 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator loop-back modes the xrt83l30 supports several loop-back modes under both hardware and host control. in hardware mode the two loop[1:0] pins control the loop-back functions according to table 14 . in host mode the loop-back functions are controlled by th e three loop[2:0] interface bits. the liu can be programmed according to table 15 . local analog loop-back (aloop) with local analog loop-back activated, the transmit data at ttip and tring are looped-back to the analog input of the receiver. external inputs at rtip/rring in this mode are ignored while valid transmit data continues to be sent to the line. local analog loop-ba ck exercises most of the functional blocks of the xrt83l30 including the jitter attenuator which can be sele cted in either the transmit or receive paths. local analog loop-back is shown in figure 20 . in this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path. t able 14: l oop - back control in h ardware mode loop1 loop0 l oop - back m ode 0 0 none 0 1 analog 1 0 remote 1 1 digital t able 15: l oop - back control in h ost mode loop2 loop1 loop0 l oop - back m ode 0 x x none 1 0 0 dual 1 0 1 analog 1 1 0 remote 1 1 1 digital f igure 20. l ocal a nalog l oop - back signal flow rx data & clock recovery decoder tpos tneg tclk rclk rpos rneg tx encoder timing control ja ttip tring rtip rring
xrt83l30 39 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 remote loop-back (rloop) with remote loop-back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using rclk as transmit timing. in this mode transmit clock and data are ignored, while rclk and re ceive data will continue to be available at their respective output pins. remote loop-back with jitter attenuator select ed in the receive path is shown in figure 21 . in the remote loop-back mode if the jitter attenuator is selected in the transmit path, the receive data from the clock and data recovery block is looped back to the trans mit path and is applied to the jitter attenuator using rclk as transmit timing. in this mode the transmit clo ck and data are also ignored, while rclk and received data will continue to be available at their respective output pins. remote loop-back wit h the jitter attenuator selected in the transmit path is shown in figure 22 . f igure 21. r emote l oop - back mode with jitter attenuator selected in receive path f igure 22. r emote l oop - back mode with jitter attenuator selected in t ransmit path tx decoder timing control rx data & clock recovery tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring ja tx decoder timing control rx clock & data recovery ja tpos tneg tclk rclk rpos rneg encoder ttip trin g rtip rrin g
xrt83l30 40 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator digital loop-back (dloop) digital loop-back or local loop-back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder /decoder and jitter attenuator. in this mode, receive data and clock are ignored, bu t the transmit data will be sent to the lin e uninterrupted. this loop back feature allows users to configure the line interface as a pure jitter attenuator. the digital loop-back signal flow is shown in figure 23 . dual loop-back figure 24 depicts the data flow in dual-loopback. in this mo de, selecting the jitter attenuator in the transmit path will have the same result as plac ing the jitter attenuator in the receive path. in d ual loop-back mode the recovered clock and data from the line are looped back through the transmitter to the ttip and tring without passing through the jitter attenuator. the transmit clock a nd data are looped back through the jitter attenuator to the rclk and rpos/rdata and rneg pins. f igure 23. d igital l oop - back mode with jitter attenuator selected in t ransmit path f igure 24. s ignal flow in d ual loop - back mode tx decoder timing control rx data & clock recovery ja tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring tx decoder timing control rx data & clock recovery ja tpos tneg tclk rclk rpos rneg encoder ttip tring rtip rring
xrt83l30 41 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 host mode serial interface operation xrt83l30 has a simple four wire serial interface that is compatible with ma ny of the microcontrollers available in the market. the host mode operation is enabled by connecting pin 20 (hw/ host ) to a ?low?. the serial interface provides a total of 32 ?read/write? 8-bi t registers that consists of the following signals: cs - chip select (active "low") sclk - serial clock sdi - serial data input sdo - serial data output using the microproc essor serial interface the following instructions for using the microprocessor se rial interface are best understood by referring to the diagram in figure 25 . in order to use the serial interface, a clock signal mu st be applied to the sclk input pin. the maximum sclk clock frequency is 20mhz. a read or write operation ca n then be initiated by asserting the active-low chip select ( cs ) input pin. for proper operation the cs must be asserted ?low? at least 50ns prior to the first rising edge of the sclk. once the cs pin has been asserted, the read/write operation and the target register can be specified through the serial interfac e by writing eight serial bits into the sdi input. each bit will be clocked on the rising edge of sclk.the function of t he eight bits are identified and described below: bit 1: r/ w (read/write) bit this bit is clocked into the sdi input on the first rising edge of the sclk after cs has been asserted. this bit indicates whether the current operation is a ?read? or a ?write?. a ?1? in this bit specifies a read operation, whereas a ?0? specifies a ?write? operation.
xrt83l30 42 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator bit 2 through 6:the five (5) address values (labeled a0, a1, a2, a3 and a4) the next five rising edges of the sc lk signal, clock in the 5-bit address value for the read or write operation. these five bits define the register address within xrt83l30 that the user has selected to read data from or write data to. the address bits must be supplied to the sdi input in ascending order with lsb (least significant bit) first. bit 7: (a5) the next bit a5 must be set to ?0? as shown in figure 25 . bit 8: (a6) the value of a6 is a ?don?t care?. once the first eight bits have been written into the se rial interface, the subsequent action depends on the whether the current operation is a ?read? or ?write? instruction. read operation with the last address bit ?a4? writ ten into the sdi input, the ?read? operation will proceed through an idle period lasting two sclk periods. on the rising edge of the 9th sclk the serial data output (sdo) becomes active (see figure 25 ). at this point the user can begin reading the 8-bit data (d0 through d7) stored in the interface register at address [a4,a3,a2,a1,a0], in ascending order (lsb first), on the falling edge of sclk. write operation with the last address bit (a4) written into the sdi in put, the ?write? operation w ill proceed through an idle period lasting two sclk periods. prior to the rising ed ge of the 9th sclk, the user must begin to apply the eight bit data word to the sdi input. the serial interface will latch this dat a on the rising edge of sclk. the serial data (d0 through d7) should enter the sdi input in ascending order with the lsb first. serial interface register description the serial interface consists of 32 8-bit register loca tions. the microprocessor register address map and bit map are described in table 16 and table 17 respectively. the function of the individual bits are described in table 18 through table 36 . f igure 25. m icroprocessor s erial i nterface d ata s tructure 5 6 7 8 1 2 3 4 13 14 15 16 9 10 11 12 r/w ao a1 a2 a3 a4 0 a6 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 cs sclk sdi sdo high z high z
xrt83l30 43 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 16: m icroprocessor r egister a ddress r egister n umber r egister a ddress f unction hex binary 0 - 18 0x00 - 0x12 00000 - 10010 command and control registers 19 - 21 0x13 - 0x15 10011 - 10101 reserved 22 - 29 0x16 - 0x1d 10110 - 11101 r/w registers reserved for testing purpose 30 0x1e 11110 device "id" 31 0x1f 11111 device "revision id" t able 17: m icroprocessor r egister b it m ap r eg . # a ddress r eg . t ype b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 control registers 0 00000 hex 0x00 r/w reserved reserved reserved eqc4 eqc3 eqc2 eqc1 eqc0 1 00001 hex 0x01 r/w rxtsel txtsel tersel1 tersel0 jasel1 jasel0 jabw fifos 2 00010 hex 0x02 r/w rxon txtest2 txtest1 txtest0 txon loop2 loop1 loop0 3 00011 hex 0x03 r/w nlcde1 nlcde0 codes rxres1 rxres0 insbpv reserved tratio 4 00100 hex 0x04 r/w gie dmoie flsie lcvie nlcdie aisdie rlosie qrpdie 5 00101 hex 0x05 ro reserved dmo fls lcv nlcd aisd rlos qrpd 6 00110 hex 0x06 rur reserved dmois flsis lcvis nlcdis aisdis rlosis qrpdis 7 00111 hex 0x07 ro reserved reserved clos5 clos4 clos3 clos2 clos1 clos0 8 01000 hex 0x08 r/w x b6s1 b5s1 b4s1 b3s1 b2s1 b1s1 b0s1 9 01001 hex 0x09 r/w x b6s2 b5s2 b4s2 b3s2 b2s2 b1s2 b0s2 10 01010 hex 0x0a r/w x b6s3 b5s3 b4s3 b3s3 b2s3 b1s3 b0s3 11 01011 hex 0x0b r/w x b6s4 b5s4 b4s4 b3s4 b2s4 b1s4 b0s4 12 01100 hex 0x0c r/w x b6s5 b5s5 b4s5 b3s5 b2s5 b1s5 b0s5 13 01101 hex 0x0d r/w x b6s6 b5s6 b4s6 b3s6 b2s6 b1s6 b0s6 14 01110 hex 0x0e r/w x b6s7 b5s7 b4s7 b3s7 b2s7 b1s7 b0s7
xrt83l30 44 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator 15 01111 hex 0x0f r/w x b6s8 b5s8 b4s8 b3s8 b2s8 b1s8 b0s8 16 10000 hex 0x10 r/w sr/ dr ataos rclke tclke datap reserved reserved sreset 17 10001 hex 0x11 r/w reserved clksel2 clksel1 clksel0 mclkrate rxmute exlos ict 18 10010 hex 0x12 r/w gauge1 gauge0 txoncntl tercntl sl_1 sl_0 eqg_1 eqg_0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 reset = 0 unused registers 19 10011 hex 0x13 r/w reserved reserved reserved reserved reserved reserved reserved reserved 20 10100 hex 0x14 r/w reserved reserved reserved reserved reserved reserved reserved reserved 21 10101 hex 0x15 r/w reserved reserved reserved reserved reserved reserved reserved reserved test registers 22 10110 hex 0x16 r/w test byte 0 23 10111 hex 0x17 r/w test byte 1 24 11000 hex 0x18 r/w test byte 2 25 11001 hex 0x19 r/w test byte 3 26 11010 hex 0x1a r/w test byte 4 27 11011 hex 0x1b r/w test byte 5 28 11100 hex 0x1c r/w test byte 6 29 11101 hex 0x1d r/w test byte 7 id registers 30 11110 hex 0x1e device id ? f9 31 11111 hex 0x1f device "revision id" t able 17: m icroprocessor r egister b it m ap r eg . # a ddress r eg . t ype b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
xrt83l30 45 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 18: m icroprocessor r egister #0 bit description r egister a ddress 00000 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6 reserved r/w 0 d5 reserved r/w 0 d4 eqc4 equalizer control bit 4: this bit together with eqc[3:0] are used for controlling transmit pulse shaping, transmit line build-out (lbo), receive monitoring and also t1 or e1 mode of operation. see table 5 for description of equalizer control bits. r/w 0 d3 eqc3 equalizer control bit 3: see bit d4 description for function of this bit r/w 0 d2 eqc2 equalizer control bit 2: see bit d4 description for function of this bit r/w 0 d1 eqc1 equalizer control bit 1: see bit d4 description for function of this bit r/w 0 d0 eqc0 equalizer control bit 0: see bit d4 description for function of this bit r/w 0
xrt83l30 46 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 19: m icroprocessor r egister #1 bit description r egister a ddress 00001 f unction r egister t ype r eset v alue b it # n ame d7 rxtsel receiver termination select: in host mode, this bit is used to select between the internal and external line termination modes for the receiver according to the following table: r/w 0 d6 txtsel transmit termination select: in host mode, this bit is used to select between the internal and external line termination modes for the transmitter according to the following table: r/w 0 d5 tersel1 termination impedance select bit 1: in the host mode and in the internal termination mode (txt - sel=?1? and rxtsel=?1?), tersel[1:0] control the transmit and receive termination impedance according to the following table: in the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed resistor (see description for rxres[1:0] bits). in the internal termination mode, the transmitter output should be ac coupled to the transformer. r/w 0 d4 tersel0 termination impedance select bit 0: see description of bit d5 for the function of this bit. r/w 0 rxtsel rx termination 0 1 external internal txtsel tx termination 0 1 external internal 0 1 1 0 1 1 0 0 100 ? 110 ? 75 ? 120 ? termination tersel1 tersel0
xrt83l30 47 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 d3 jasel1 jitter attenuator select bit 1: the jasel1 and jasel0 bits are used to disable or place the jitter attenuator in the transmit or receive path. r/w 0 d2 jasel0 jitter attenuator select bit 0: see description of bit d3 for the function of this bit. r/w 0 d1 jabw jitter attenuator bandwidth select: in e1 mode, set this bit to "1" to select a 1.5hz bandwidth for the jitter attenuator in e1 mode. the fifo length will be automati - cally set to 64 bits. set this bit to "0" to select 10hz bandwidth for the jitter attenua - tor in e1 mode. in t1 mode the jitter attenuator bandwidth is permanently set to 3hz, and the state of this bit has no effect on the bandwidth. r/w 0 d0 fifos fifo size select: see table of bit d1 above for the function of this bit. r/w 0 t able 19: m icroprocessor r egister #1 bit description jasel1 bit d3 jasel0 bit d2 0 0 0 1 1 0 1 1 ja path ja disabled ja in transmit path ja in receive path ja in receive path 0 1 0 1 0 1 0 1 fifos_n bit d0 0 0 1 1 0 0 1 1 jabw bit d1 t1 t1 t1 t1 e1 e1 e1 e1 mode 32 64 32 64 32 64 64 64 fifo size 3 3 3 3 10 10 1.5 1.5 ja b-w hz
xrt83l30 48 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 20: m icroprocessor r egister #2 bit description r egister a ddress 00010 f unction r egister t ype r eset v alue b it # n ame d7 rxon receiver on: writing a ?1? into this bit location turns on the receive section. writing a ?0? shuts off the receiver section. in this mode, rtip and rring driver outputs will be tri-stated for power reduction or redundancy applications. default is "0", off. r/w 0 d6 txtest2 transmit test pattern bit 2 : this bit together with txtest1 and txtest0 are used to generate and transmit test patterns according to the following table: tdqrss (transmit/detect quasi-random signal): this con - dition, when activated, enables quasi-random signal source generation and detection. in a t1 system qrss pattern is a 2 20 - 1 pseudo-random bit sequence (prbs) with no more than 14 consecutive zeros. in a e1 system, qrss is a 2 15 -1 prbs pat - tern. taos (transmit all ones): activating this condition enables the transmission of an all ones pattern. tclk must not be tied "low". tluc (transmit network loop-up code): activating this con - dition enables the network loop-up code of "00001" to be trans - mitted to the line. when network loop-up code is being transmitted, the xrt83l30 will ignore the automatic loop-code detection and remote loop-back activation (nlcde1 =?1?, nlcde0 =?1?, if activated) in order to avoid activating remote digital loop-back automatically when the remote terminal responds to the loop-back request. tldc (transmit network loop-down code): activating this condition enables the network loop-down code of "001" to be transmitted to the line. r/w 0 d5 txtest1 transmit test pattern bit 1: see description of bit d6 for the function of this bit. r/w 0 d4 txtest0 transmit test pattern bit 0: see description of bit d6 for the function of this bit. r/w 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 transmit data taos tluc tldc test pattern txtest1 txtest0 txtest2 1 0 1 1 1 1 0 1 1 tdqrss tdqrss & invqrss tdqrss & insber tdqrss & invqrss & in s
xrt83l30 49 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 d3 txon transmitter on: writing a "1" into this bit location turns on the transmit section. a ?0? in this bit location, shuts off the transmit - ter. in this mode the ttip and tring driver outputs will be tri- stated for power reduction or redundancy applications. r/w 0 d2 loop2 loop-back control bit 2: this bit together with the loop1 and loop0 bits control the loop-back modes of the chip according to the following table: r/w 0 d1 loop1 loop-back control bit 1: see description of bit d2 for the func - tion of this bit. r/w 0 d0 loop0 loop-back control bit 0: see description of bit d2 for the func - tion of this bit. r/w 0 t able 20: m icroprocessor r egister #2 bit description loop2 0 1 1 1 1 loop1 x 0 0 1 1 loop0 x 0 1 0 1 loop-back mode no loop-back dual loop-back analog loop-back remote loop-back digital loop-back
xrt83l30 50 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 21: m icroprocessor r egister #3 bit description r egister a ddress 00011 f unction r egister t ype r eset v alue b it # n ame d7 nlcde1 network loop code detection enable bit 1: this bit together with nlcde0, control the loop-code detection according to the following table: when nlcde1=?0? and nclde0=?1?, or nlcde1=?1? and nlcde0=?0?, the chip is manually programed to monitor the receive data for the loop-up or loop-down code respectively. when the presence of the ?00001? or ?001? pattern is detected for more than 5 seconds, the status of the nlcd bit is set to ?1? and if the nlcd interrupt is enabled an interrupt is initiated. the host has the option to control the loop-back function manually. setting the nlcde1=?1? and nlcde0=?1? enables the auto - matic loop-code detection and remote-loop-back activation mode. as this mode is initiated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to monitor the receive data for the loop-up code. if the ?00001? pattern is detected for longer than 5 seconds, the nlcd bit is set to ?1?, remote loop-back is activated and the chip is automatically pro - gramed to monitor the receive data for the loop-down code. the nlcd bit stays set even after the chip stops receiving the loop- up code. the remote loop-back condition is removed when the chip receives the loop-down code for more than 5 seconds or if the automatic loop-code detection mode is terminated. r/w r/w 0 0 d6 nlcde0 network loop code detection enable bit 0: see description of bit d7 for the function of this bit. r/w 0 d5 codes encoding and decoding select: writing a ?0? to this bit selects hdb3 or b8zs encoding and decoding. writing a ?1? selects an ami coding scheme.this bit is only active when single-rail mode is selected. r/w 0 nlcde1 nlcde0 function 0 0 disable loop-code detection 0 1 detect loop-up code in receive data 1 1 automatic loop-code detection 1 0 detect loop-down code in receive data
xrt83l30 51 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 d4 rxres1 receive external resistor control pin 1: in host mode, this bit along with the rxres0 bit selects the value of the external receive fixed resistor according to the following table: r/w 0 d3 rxres0 receive external resistor control bit 0: for function of this bit see description of d4 the rxres1 bit. r/w 0 d2 insbpv insert bipolar violation: when this bit transitions from "0" to "1", a bipolar violation is inserted in the transmitted data stream. bipolar violation can be inserted either in the qrss pattern, or input data when operating in single-rail mode. the state of this bit is sampled on the rising edge of tclk. n ote : to ensure the insertion of a bipolar violation, a "0" should be written in this bit location before writing a "1". r/w 0 d1 reserved r/w 0 d0 tratio transformer ratio select: in the external termination mode, writing a ?1? to this bit selects a transformer ratio of 1:2 for the transmitter. writing a ?0? sets the transmitter transformer ratio to 1: 2.45. in the internal termination mode the transmitter trans - former ratio is permanently set to 1:2 and the state of this bit has no effect. r/w 0 t able 21: m icroprocessor r egister #3 bit description required fixed external rx resistor no external fixed resistor 60 ? 52.5 ? 37.5 ? rxres0 0 1 0 1 rxres1 0 0 1 1
xrt83l30 52 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 22: m icroprocessor r egister #4 bit description r egister a ddress 00100 f unction r egister t ype r eset v alue b it # n ame d7 gie global interrupt enable: writing a "1" into this bit, globally enables interrupt generation on the int pin. writing a "0" into this bit, globally masks a ll interrupt requests. r/w 0 d6 dmoie dmo interrupt enable: writing a "1" to this bit enables dmo interrupt generation, writing a "0" masks it. r/w 0 d5 flsie fifo limit status interrupt enable: writing a "1" to this bit enables interrupt generation when the fifo limit is within 3 bits, writing a "0" to masks it. r/w 0 d4 lcvie line code violation interrupt enable: writing a "1" to this bit enables line code violation interrupt generation, writing a "0" masks it. r/w 0 d3 nlcdie network loop-code detection interrupt enable: writing a "1" to this bit enables network loop-code detection interrupt genera - tion, writing a "0" masks it. r/w 0 d2 aisdie ais detection interrupt enable: writing a "1" to this bit enables alarm indication signal detection interrupt generation, writing a "0" masks it. r/w 0 d1 rlosie receive loss of signal interrupt enable: writing a "1" to this bit enables loss of receive signal interrupt generation, writing a "0" masks it. r/w 0 d0 qrpdie qrss pattern detectio n interrupt enable: writing a "1" to this bit enables qrss pattern detection interrupt generation, writing a "0" masks it. r/w 0
xrt83l30 53 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 23: m icroprocessor r egister #5 bit description r egister a ddress 00101 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 dmo driver monitor output: this bit is set to a "1" to indicate trans - mit driver failure is detected. the value of this bit is based on the current status of dmo. if the dmoie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d5 fls fifo limit status: this bit is set to a "1" to indicate that the jitter attenuator read/write fifo pointers are within +/- 3 bits. if the flsie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d4 lcv line code violation: this bit is set to a "1" to indicate that the receiver is currently detecting a line code violation or an exces - sive number of zeros in the b8zs or hdb3 modes. if the lcvie bit is enabled, any transition on th is bit will generate an interrupt. ro 0
xrt83l30 54 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator d3 nlcd network loop-code detection: this bit operates differently in the manual or the automatic net - work loop-code detection modes. in the manual loop-code detection mode (nlcde1 =?0? and nlcde0 =?1?, or nlcde1 =?1? and nlcde0 =?0?) this bit gets set to ?1? as soon as the loop-up (?00001?) or loop-down (?001?) code is detected in the receive data for longer than 5 sec - onds. the nlcd bit stays in the ?1? state for as long as the chip detects the presence of the loop-code in the receive data and it is reset to ?0? as soon as it stops receiving it. in this mode if the nlcd interrupt is enabled the chip will initiate an interrupt on every transition of the nlcd. when the automatic loop-code detection mode (nlcde1 =?1? and nlcde0 =?1?) is initiated, the state of the nlcd interface bit is reset to ?0? and the chip is programmed to monitor the receive input data for the loop-up code. this bit is set to a ?1? to indicate that the network loop code is detected for more than 5 sec - onds. simultaneously the remote loop-back condition is auto - matically activated and the chip is programmed to monitor the receive data for the network loop-down code. the nlcd bit stays in the ?1? state for as long as the remote loop-back condi - tion is in effect even if the chip stops receiving the loop-up code. remote loop-back is removed if the chip detects the ?001? pattern for longer than 5 seconds in the receive data. detecting the ?001? pattern also results in resetting the nlcd interface bit and initiating an interrupt provided the nlcd inter - rupt enable bit it active. when programmed in the automatic detection mode, the nlcd interface bit stays ?high? for the entire time the remote loop-back is active and initiates an interrupt anytime the status of the nlcd bit changes. in this mode the host can monitor the state of the nlcd bit to determine if the remote loop-back is activated. ro 0 d2 aisd alarm indication signal detect: this bit is set to a "1" to indi - cate all ones signal is detected by the receiver. the value of this bit is based on the current status of alarm indication signal detector. if the aisdie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d1 rlos receive loss of signal: this bit is set to a "1" to indicate that the receive input signal is lost. the value of this bit is based on the current status of the receive input signal. if the rlosie bit is enabled, any transition on this bit will generate an interrupt. ro 0 d0 qrpd quasi-random pattern detection: this bit is set to a "1" to indi - cate the receiver is currently in synchronization with qrss pat - tern. the value of this bit is based on the current status of quasi- random pattern detector of. if the qrpdie bit is enabled, any transition on this bit will generate an interrupt. ro 0 t able 23: m icroprocessor r egister #5 bit description
xrt83l30 55 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 24: m icroprocessor r egister #6 bit description r egister a ddress 00110 f unction r egister t ype r eset v alue b it # n ame d7 reserved rur 0 d6 dmois driver monitor output interrupt status: this bit is set to a "1" every time when dmo status has changed since last read. rur 0 d5 flsis fifo limit interrupt status: this bit is set to a "1" every time when fifo limit (read/write pointer with +/- 3 bits apart) status has changed since last read. rur 0 d4 lcvis line code violation interrupt status: this bit is set to a "1" every time when lcv status has changed since last read. rur 0 d3 nlcdis network loop-code detection interrupt status: this bit is set to a "1" every time when nlcd status has changed since last read. rur 0 d2 aisdis ais detection in terrupt status: this bit is set to a "1" every time when aisd status has changed since last read. rur 0 d1 rlosis receive loss of signal interrupt status: this bit is set to a "1" every time rlos status has changed since last read. rur 0 d0 qrpdis quasi-random pattern detection interrupt status: this bit is set to a "1" every time when qrpd status has changed since last read. rur 0
xrt83l30 56 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 25: m icroprocessor r egister #7 bit description r egister a ddress 00111 f unction r egister t ype r eset v alue b it # n ame d7 reserved ro 0 d6 reserved ro 0 d5 clos5 cable loss bit 5: clos[5:0] are the six bits receiver for selec - tive equalizer setting which is also a binary word that represents the cable attenuation indication within 1db. clos5 is the most significant bit (msb) and clos0 is the least significant bit (lsb). ro 0 d4 clos4 cable loss bit 4: see description of d5 for function of this bit. ro 0 d3 clos3 cable loss bit 3: see description of d5 for function of this bit. ro 0 d2 clos2 cable loss bit 2: see description of d5 for function of this bit. ro 0 d1 clos1 cable loss bit 1: see description of d5 for function of this bit. ro 0 d0 clos0 cable loss bit 0: see description of d5 for function of this bit. ro 0 t able 26: m icroprocessor r egister #8 bit description r egister a ddress 01000 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s1 - b0s1 arbitrary transmit pulse shape, segment 1 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the first time segment. b6s1 -b0s1 is in signed magni - tude format with b6s1 as the sign bit and b0s1 as the least sig - nificant bit (lsb). r/w 0
xrt83l30 57 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 27: m icroprocessor r egister #9 bit description r egister a ddress 01001 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s2 - b0s2 arbitrary transmit pulse shape, segment 2 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the second time segment. b6s2 -b0s2 is in signed mag - nitude format with b6s2 as the sign bit and b0s2 as the least significant bit (lsb). r/w 0 t able 28: m icroprocessor r egister #10 bit description r egister a ddress 01010 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s3 - b0s3 arbitrary transmit pulse shape, segment 3 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the thrd time segment. b6s3 -b0s3 is in signed magni - tude format with b6s3 as the sign bit and b0s3 as the least sig - nificant bit (lsb). r/w 0
xrt83l30 58 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 29: m icroprocessor r egister #11 bit description r egister a ddress 01011 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s4 - b0s4 arbitrary transmit pulse shape, segment 4 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the fourth time segment. b6s4 -b0s4 is in signed magni - tude format with b6s4 as the sign bit and b0s4 as the least sig - nificant bit (lsb). r/w 0 t able 30: m icroprocessor r egister #12 bit description r egister a ddress 01100 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s5 - b0s5 arbitrary transmit pulse shape, segment 5 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the fith time segment. b6s5 -b0s5 is in signed magni - tude format with b6s5 as the sign bit and b0s5 as the least sig - nificant bit (lsb). r/w 0
xrt83l30 59 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 31: m icroprocessor r egister #13 bit description r egister a ddress 01101 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s6 - b0s6 arbitrary transmit pulse shape, segment 6 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the sixth time segment. b6s6 -b0s6 is in signed magni - tude format with b6s6 as the sign bit and b0s6 as the least sig - nificant bit (lsb). r/w 0 t able 32: m icroprocessor r egister #14 bit description r egister a ddress 01110 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s7 - b0s7 arbitrary transmit pulse shape, segment 7 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the seventh time segment. b6s7 -b0s7 is in signed mag - nitude format with b6s7 as the sign bit and b0s7 as the least significant bit (lsb). r/w 0
xrt83l30 60 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 33: m icroprocessor r egister #15 bit description r egister a ddress 01111 f unction r egister t ype r eset v alue b it # n ame d7 reserved r/w 0 d6-d0 b6s8 - b0s8 arbitrary transmit pulse shape, segment 8 the shape of the transmitted pulse can be made user program - mable by selecting "arbitrary pulse" mode, see table 5 . the arbitrary pulse is divided into eight time segments whose com - bined duration is equal to one period of mclk. this 7 bit number represents the amplitude of the arbitrary pulse during the eighth time segment. b6s8 -b0s8 is in signed magni - tude format with b6s8 as the sign bit and b0s8 as the least sig - nificant bit (lsb). r/w 0
xrt83l30 61 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 34: m icroprocessor r egister #16 bit description r egister a ddress 10000 n ame f unction r egister t ype r eset v alue b it # d7 sr/ dr single-rail/dual-rail select: writing a "1" to this bit configures the xrt83l30 to operate in the single-rail mode. writing a "0" configures the xrt83l30 to operate in dual-rail mode. r/w 0 d6 ataos automatic transmit al l ones upon rlos: writing a "1" to this bit enables the automatic transmission of all ones data to the line. writing a "0" disables this feature. r/w 0 d5 rclke receive clock edge: writing a "1" to this bit selects receive out - put data to be updated on the negative edge of rclk. writing a "0" selects data to be updated on the positive edge of rclk. r/w 0 d4 tclke transmit clock edge: writing a "0" to this bit selects transmit data at tpos/tdata and tneg to be sampled on the falling edge of tclk. writing a "1" selects the rising edge of the tclk for sampling. r/w 0 d3 datap data polarity: writing a "0" to this bit selects transmit input and receive output data of the xrt83l30 to be active "high". writing a "1" selects an active "low" state. r/w 0 d2 reserved r/w 0 d1 reserved r/w 0 d0 sreset software reset p registers: writing a "1" to this bit longer than 10 s resets all internal state machines r/w 0
xrt83l30 62 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 35: m icroprocessor r egister #17 bit description r egister a ddress 10001 n ame f unction r egister t ype r eset v alue b it # d7 reserved r/w 0 d6 clksel2 clock select inputs for master clock synthesizer bit 2 : in host mode, clksel[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an external accurate clock source according to the fol - lowing table: in hardware mode the state of these bits are ignored and the master frequency pll is controlled by the corresponding hard - ware pins. r/w 0 d5 clksel1 clock select inputs for master clock synthesizer bit 1: see description of bit d6 for function of this bit. r/w 0 d4 clksel0 clock select inputs for master clock synthesizer bit 0: see description of bit d6 for function of this bit. r/w 0 2048 2048 2048 1544 mclke1 khz 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 mclkt1 khz 1544 x x x 1544 x x x x x x x 2048 1544 2048 clkout khz 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 clksel0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 clksel1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 clksel2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 x x 2048 1544 0 1 0 1 mclkrate 1 0 1 0 0 1 0 1 1 0 1 0 0 1
xrt83l30 63 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 d3 mclkrate master clock rate select: the state of this bit programs the master clock synthesizer to generate the t1/j1 or e1 clock. the master clock synthesizer will generate the e1 clock when mclkrate = ?0?, and the t1/j1 clock when mclkrate = ?1?. r/w 0 d2 rxmute receive output mute: writing a "1" to this bit, mutes receive outputs at rpos/rdata and rneg/lcv pins to a "0" state. n ote : rclk is not muted. r/w 0 d1 exlos extended los: writing a "1" to this bit extends the number of zeros at the receive input before rlos is declared to 4096 bits. writing a "0" reverts to the normal mode (175+75 bits for t1 and 32 bits for e1). r/w 0 d0 ict in-circuit-testing: writing a "1" to this bit configures all the out - put pins of the chip in "high" impedance mode for in-circuit-test - ing. setting ict bit to ?1? is equivalent to connecting the hardware ict pin to ground. r/w 0 t able 36: m icroprocessor r egister #18 bit description r egister a ddress 10010 n ame f unction r egister t ype r eset v alue b it # d7 gauge1 wire gauge selector bit 1 this bit along with bit d6 are used to select wire gauge size as shown in the table below. r/w 0 d6 gauge0 wire gauge selector bit 0 see bit d7. r/w 0 d5 txoncntl transmit on control. in host mode, setting this bit to ?1? transfers the control of the transmit on/off function to the txon hardware control pin. n ote : this provides a faster on/off capability for redundancy application. r/w 0 d4 tercntl termination control: in host mode, setting this bit to ?1? transfers the control of the rxtsel to the rxtsel hardware control pin. n ote : this provides a faster on/off capability for redundancy application. r/w 0 t able 35: m icroprocessor r egister #17 bit description gauge1 0 1 1 0 gauge0 0 1 0 1 wire size 22 and 24 gauge 26 gauge 24 gauge 22 gauge
xrt83l30 64 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator d3 sl_1 slicer level control bit 1: this bit and bit d2 control the slic - ing level for the slicer per the following table. r/w 0 d2 sl_0 slicer level control bit 0: see description bit d3. r/w 0 d1 eqg_1 equalizer gain control bit 1: this bit together with bit d0 control the gain of the equalizer as shown in the table below. r/w 0 d0 eqg_0 equalizer gain control bit 0: see description of bit d1. r/w 0 t able 36: m icroprocessor r egister #18 bit description sl_1 sl_0 0 0 0 1 1 0 1 1 slicer mode normal decrease by 5% from normal increase by 5% from normal normal eqg_1 eqg_0 0 0 0 1 1 0 1 1 equalizer gain normal reduce gain by 1 db reduce gain by 3 db normal
xrt83l30 65 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 electrical characteristics t able 37: a bsolute m aximum r atings storage temperature...............-65c to +150c operating temperature............. -40c to +85c supply voltage............................-0.5v to +3.8v vin................................................-0.5 to +5.5v t able 38: dc d igital i nput and o utput e lectrical c haracteristics vdd=3.3v5%, t a =25c, unless otherwise specified p arameter s ymbol m in t yp m ax u nits power supply voltage vdd 3.13 3.3 3.46 v input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage @ ioh = 2.0ma v oh 2.4 - - v output low voltage @iol = 2.0ma v ol - - 0.4 v input leakage current (except input pins with pull-up or pull- down resistor). i l - - 10 a input capacitance c i - 5.0 - pf output load capacitance c l - - 25 pf t able 39: xrt83l30 p ower c onsumption vdd=3.3v5%, t a =25c, i nternal i mpedance , unless otherwise specified m ode s upply v oltage i mpedance termination r esistor t ransformer r atio t yp m ax u nit t est c onditions r eceiver t ransmitter e1 3.3v 75 ? internal 1:1 1:2 298 350 mw 100% ?1?s? e1 3.3v 120 ? internal 1:1 1:2 276 325 mw 100% ?1?s? t1 3.3v 100 ? internal 1:1 1:2 310 365 mw 100% ?1?s? --- 3.3v --- external --- --- 72 85 mw all transmitters off
xrt83l30 66 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 40: e1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in t yp m ax u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 10 15 12.5 175 20 255 db db cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? applica - tion. with -18db interference signal added. receiver sensitivity (long haul with cable loss) nominal extended 0 0 36 43 db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? applica - tion. with -18db interference signal added. input impedance 13 k ? input jitter tolerance: 1 hz 10khz-100khz >64 0.4 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 20 0.5 khz db itu g.736 jitter attenuator corner fre - quency (-3db curve) (jabw=0) (jabw=1) - 10 1.5 - hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 - - db db db itu-g.703
xrt83l30 67 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 41: t1 r eceiver e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in t yp m ax u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 100 15 12.5 175 20 - 250 - - db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 db with nominal pulse amplitude of 3.0v for 100 ? termination receiver sensitivity (long haul with cable loss) 0 - 36 db db with nominal pulse amplitude of 3.0v for 100 ? termination input impedance 13 - k ? jitter tolerance: 1hz 10khz - 100khz 138 0.4 - - - - uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 9.8 - 0.1 khz db tr-tsy-000499 jitter attenuator corner fre - quency (-3db curve) - 3 hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 20 25 25 - - - db db db t able 42: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss g.703/ch-ptt ets 300166 51-102khz 8db 6db 102-2048khz 14db 8db 2048-3072khz 10db 8db
xrt83l30 68 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator t able 43: e1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in t yp m ax u nit t est c onditions ami output pulse amplitude: 75 ? application 120 ? application 2.185 2.76 2.37 3.0 2.555 3.24 v v transformer with 1:2 ratio and 9.1 ? resistor in series with each end of pri - mary. output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 jitter added by the transmitter out - put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 8 14 10 - - - - - - db db db etsi 300 166, chptt t able 44: t1 t ransmitter e lectrical c haracteristics vdd=3.3v5%, t a = -40 to 85c, unless otherwise specified p arameter m in t yp m ax u nit t est c onditions ami output pulse amplitude: 2.5 3.0 3.5 v tansformer with 1:2.45 ratio and mea - sured at dsx-1 output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance - - + 200 mv ansi t1.102 jitter added by the transmitter out - put - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 15 15 15 - - - db db db
xrt83l30 69 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 f igure 26. itu g.703 p ulse t emplate t able 45: t ransmit p ulse m ask s pecification test load impedance 75 ? resistive (coax) 120 ? resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note ? v corresponds to the nominal peak value. 20% 20%
xrt83l30 70 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator f igure 27. dsx-1 p ulse t emplate ( normalized amplitude ) t able 46: dsx1 i nterface i solated p ulse m ask and c orner p oints m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v
xrt83l30 71 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 t able 47: ac e lectrical c haracteristics (t a =25c, vdd=3.3v5%, unless otherwise specified ) p arameter s ymbol m in t yp m ax u nits e1 mclk clock frequency - 2.048 - mhz t1 mclk clock frequency - 1.544 - mhz mclk clock duty cycle 40 - 60 % mclk clock tolerance - 50 - ppm tclk duty cycle t cdu 30 50 70 % transmit data setup time t su 50 - - ns transmit data hold time t ho 30 - - ns tclk rise time(10%/90%) t clkr - - 40 ns tclk fall time(90%/10%) t clkf - - 40 ns rclk duty cycle r cdu 45 50 55 % receive data setup time r su 150 - - ns receive data hold time r ho 150 - - ns rclk to data delay r dy - - 40 ns rclk rise time(10%/90%) with 25pf loading. rclk r - - 40 ns rclk fall time(90%/10%) with 25pf loading. rclk f 40 ns f igure 28. t ransmit c lock and i nput d ata t iming tclk r tclk f tclk tpos/tdata or tneg t su t ho
xrt83l30 72 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator f igure 29. r eceive c lock and o utput d ata t iming rclk r rclk f rclk rpos or rneg r dy r ho
xrt83l30 73 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 package dimensions 64 lead thin quad flat pack (10 x 10 x 1.4 mm tqfp) rev. 3.00 note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d 1 0.390 0.398 9.90 10.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 48 33 32 17 116 49 64 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xrt83l30 74 rev. 1.0.1 single-channel t1/e1/j1 lh/sh transceiver with clock recovery and jitter attenuator ordering information revision history rev. a1.0.0 ad vanced version. rev. p1.1.0 preliminary release. rev. p1.2.0 modified microprocessor tables, moved va rious functions. added ghci_n, sl_1, sl_0, eqg_1 eqg_0, gauge1 and gauge0 to cont rol global register 18. separated microprocessor description table by register number. moved absolute maximum and dc el ectrical characteristics before ac electrical characteristics. replaced tbd?s in electrical ables. reformated table of contents. rev. p1.2.1 renamed fifo pin to gauge, edited defini tion and edited defintion of jasel[1:0] to reflect the fifo size is selected by the jitter attenuator select. rev. p1.2.2 redefined bits d3, d2 and d0 of register 1, in combination these bits set the jitter attenuator path and fifo size. rev. p1.2.3 added definitions to dual function pins in the pin description section. rev p1.2.4 added jabw, jasel 1 and jasel0 table in pin list and jitter attenuator section. corrected typos in features, figures 7, 8, 9 and 11. added jitter attenuator tables in microprocessor register tables. rev. p1.2.5 table 18, 23, 24, 25 change gchie to gi e, ghci and gchis to reserved. corrected package outline drawing. rev. p1.2.6 tercntl (pin 46) func tion removed. bit 7 of microproce ssor register #2 was insber, is now reserved. bit 1 of micropro cessor register #3 was invqrss, is now reserved. new description for bits d6 - d0 in tables 27 - 34 microprocessor registers. rev. p1.2.7 expanded information on receive redundancy. 2 tables and 1 figure. rev. p1.2.8 edited section on rlos rev. p1.2.9 removed tercntl from block diagram. ed it eqc[4:0] to be input only on block diagram. corrected rxmute, tclk, jabw, mckle1, clksel [2 :0], rxtsel, tersel[1:0 ], rxres[1:0], ataos, nlcd in the pin descriptions section. replaced the functional description sectio n. edits to table 18: microprocessor register bit map, table 21: microprocessor register #2 bit description, table 35: microprocessor register #16 bit description rev. p1.3.0 table 35: microprocessor register #17 bit description, edit e1 clock mclkrate= ?0? and t1/j1 clock mclkrate=?1? . rev. 1.0.0 final release. rev. 1.0.1 corrected package dimensions in ordering information table page 3. t able 48. p art # p ackage o perating temperature r ange xrt83l30iv 64 pin tqfp -40 o c to +85 o c t hermal i nformation theta - j a = 38 c/w theta j c = 7 c/w
75 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet june 2006. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xrt83l30 single-channel t1/e1/j1 lh/s h transceiver with clock reco very and jitter attenuator rev. 1.0.1 notes

▲Up To Search▲

Price & Availability of XRT83L3006

	To Download XRT83L3006 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .